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https://github.com/YosysHQ/yosys
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Various cleanups and improvements in opt_muxtree
This commit is contained in:
Clifford Wolf
parent
279a18c9a3
commit
61192514e3
1 changed files with 71 additions and 87 deletions
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@ -37,39 +37,33 @@ struct OptMuxtreeWorker
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SigMap assign_map;
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int removed_count;
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struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
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bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
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bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
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};
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struct bitinfo_t {
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int num;
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bitDef_t bit;
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SigBit bit;
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bool seen_non_mux;
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std::vector<int> mux_users;
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std::vector<int> mux_drivers;
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vector<int> mux_users;
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vector<int> mux_drivers;
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};
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std::map<bitDef_t, int> bit2num;
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std::vector<bitinfo_t> bit2info;
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dict<SigBit, int> bit2num;
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vector<bitinfo_t> bit2info;
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struct portinfo_t {
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std::vector<int> ctrl_sigs;
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std::vector<int> input_sigs;
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std::vector<int> input_muxes;
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int ctrl_sig;
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vector<int> input_sigs;
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vector<int> input_muxes;
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bool const_activated;
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bool const_deactivated;
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bool enabled;
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};
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struct muxinfo_t {
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RTLIL::Cell *cell;
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std::vector<portinfo_t> ports;
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vector<portinfo_t> ports;
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};
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std::vector<muxinfo_t> mux2info;
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std::set<int> root_muxes;
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vector<muxinfo_t> mux2info;
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vector<bool> root_muxes;
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OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
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design(design), module(module), assign_map(module), removed_count(0)
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@ -83,9 +77,10 @@ struct OptMuxtreeWorker
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// .mux_users
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// .mux_drivers
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// Populate mux2info[].ports[]:
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// .ctrl_sigs
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// .ctrl_sig
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// .input_sigs
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// .const_activated
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// .const_deactivated
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for (auto cell : module->cells())
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{
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if (cell->type == "$mux" || cell->type == "$pmux")
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@ -102,13 +97,13 @@ struct OptMuxtreeWorker
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RTLIL::SigSpec sig = sig_b.extract(i*sig_a.size(), sig_a.size());
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RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
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portinfo_t portinfo;
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portinfo.ctrl_sig = sig2bits(ctrl_sig, false).front();
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for (int idx : sig2bits(sig)) {
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add_to_list(bit2info[idx].mux_users, mux2info.size());
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add_to_list(portinfo.input_sigs, idx);
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}
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for (int idx : sig2bits(ctrl_sig))
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add_to_list(portinfo.ctrl_sigs, idx);
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portinfo.const_activated = ctrl_sig.is_fully_const() && ctrl_sig.as_bool();
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portinfo.const_deactivated = ctrl_sig.is_fully_const() && !ctrl_sig.as_bool();
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portinfo.enabled = false;
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muxinfo.ports.push_back(portinfo);
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}
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@ -118,7 +113,9 @@ struct OptMuxtreeWorker
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add_to_list(bit2info[idx].mux_users, mux2info.size());
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add_to_list(portinfo.input_sigs, idx);
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}
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portinfo.ctrl_sig = -1;
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portinfo.const_activated = false;
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portinfo.const_deactivated = false;
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portinfo.enabled = false;
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muxinfo.ports.push_back(portinfo);
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@ -162,6 +159,7 @@ struct OptMuxtreeWorker
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log(" Evaluating internal representation of mux trees.\n");
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dict<int, pool<int>> mux_to_users;
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root_muxes.resize(mux2info.size());
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for (auto &bi : bit2info) {
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for (int i : bi.mux_drivers)
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@ -170,23 +168,24 @@ struct OptMuxtreeWorker
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if (!bi.seen_non_mux)
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continue;
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for (int mux_idx : bi.mux_drivers)
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root_muxes.insert(mux_idx);
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root_muxes.at(mux_idx) = true;
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}
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for (auto &it : mux_to_users)
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if (GetSize(it.second) > 1)
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root_muxes.insert(it.first);
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root_muxes.at(it.first) = true;
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for (int mux_idx : root_muxes) {
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log(" Root of a mux tree: %s\n", log_id(mux2info[mux_idx].cell));
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eval_root_mux(mux_idx);
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}
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for (int mux_idx = 0; mux_idx < GetSize(root_muxes); mux_idx++)
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if (root_muxes.at(mux_idx)) {
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log(" Root of a mux tree: %s\n", log_id(mux2info[mux_idx].cell));
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eval_root_mux(mux_idx);
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}
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log(" Analyzing evaluation results.\n");
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for (auto &mi : mux2info)
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{
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std::vector<int> live_ports;
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vector<int> live_ports;
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for (int port_idx = 0; port_idx < GetSize(mi.ports); port_idx++) {
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portinfo_t &pi = mi.ports[port_idx];
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if (pi.enabled) {
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@ -247,15 +246,7 @@ struct OptMuxtreeWorker
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}
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}
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bool list_is_subset(const std::vector<int> &sub, const std::vector<int> &super)
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{
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for (int v : sub)
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if (!is_in_list(super, v))
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return false;
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return true;
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}
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bool is_in_list(const std::vector<int> &list, int value)
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bool is_in_list(const vector<int> &list, int value)
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{
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for (int v : list)
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if (v == value)
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@ -263,15 +254,15 @@ struct OptMuxtreeWorker
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return false;
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}
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void add_to_list(std::vector<int> &list, int value)
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void add_to_list(vector<int> &list, int value)
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{
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if (!is_in_list(list, value))
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list.push_back(value);
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}
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std::vector<int> sig2bits(RTLIL::SigSpec sig, bool skip_non_wires = true)
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vector<int> sig2bits(RTLIL::SigSpec sig, bool skip_non_wires = true)
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{
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std::vector<int> results;
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vector<int> results;
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assign_map.apply(sig);
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for (auto &bit : sig)
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if (bit.wire != NULL) {
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@ -292,57 +283,58 @@ struct OptMuxtreeWorker
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struct knowledge_t
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{
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// database of known inactive signals
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// the 2nd integer is a reference counter used to manage the
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// the payload is a reference counter used to manage the
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// list. when it is non-zero the signal in known to be inactive
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std::map<int, int> known_inactive;
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vector<int> known_inactive;
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// database of known active signals
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// the 2nd dimension is the list of or-ed signals. so we know that
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// for each i there is a j so that known_active[i][j] points to an
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// active control signal.
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std::vector<std::vector<int>> known_active;
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vector<int> known_active;
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// this is just used to keep track of visited muxes in order to prohibit
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// endless recursion in mux loops
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std::set<int> visited_muxes;
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vector<bool> visited_muxes;
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};
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void eval_mux_port(knowledge_t &knowledge, int mux_idx, int port_idx)
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{
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muxinfo_t &muxinfo = mux2info[mux_idx];
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if (muxinfo.ports[port_idx].const_deactivated)
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return;
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muxinfo.ports[port_idx].enabled = true;
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for (size_t i = 0; i < muxinfo.ports.size(); i++) {
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if (int(i) == port_idx)
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for (int i = 0; i < GetSize(muxinfo.ports); i++) {
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if (i == port_idx)
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continue;
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for (int b : muxinfo.ports[i].ctrl_sigs)
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knowledge.known_inactive[b]++;
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if (muxinfo.ports[i].ctrl_sig >= 0)
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knowledge.known_inactive.at(muxinfo.ports[i].ctrl_sig)++;
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}
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if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
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knowledge.known_active.push_back(muxinfo.ports[port_idx].ctrl_sigs);
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knowledge.known_active.at(muxinfo.ports[port_idx].ctrl_sig)++;
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std::vector<int> parent_muxes;
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vector<int> parent_muxes;
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for (int m : muxinfo.ports[port_idx].input_muxes) {
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if (knowledge.visited_muxes.count(m) > 0)
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if (knowledge.visited_muxes[m])
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continue;
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knowledge.visited_muxes.insert(m);
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knowledge.visited_muxes[m] = true;
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parent_muxes.push_back(m);
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}
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for (int m : parent_muxes)
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if (!root_muxes.count(m))
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if (!root_muxes.at(m))
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eval_mux(knowledge, m);
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for (int m : parent_muxes)
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knowledge.visited_muxes.erase(m);
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knowledge.visited_muxes[m] = false;
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if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
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knowledge.known_active.pop_back();
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knowledge.known_active.at(muxinfo.ports[port_idx].ctrl_sig)--;
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for (size_t i = 0; i < muxinfo.ports.size(); i++) {
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if (int(i) == port_idx)
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continue;
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for (int b : muxinfo.ports[i].ctrl_sigs)
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knowledge.known_inactive[b]--;
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if (muxinfo.ports[i].ctrl_sig >= 0)
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knowledge.known_inactive.at(muxinfo.ports[i].ctrl_sig)--;
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}
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}
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@ -351,20 +343,17 @@ struct OptMuxtreeWorker
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SigSpec sig = muxinfo.cell->getPort(portname);
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bool did_something = false;
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std::vector<int> bits = sig2bits(sig, false);
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vector<int> bits = sig2bits(sig, false);
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for (int i = 0; i < GetSize(bits); i++) {
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if (bits[i] < 0)
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continue;
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if (knowledge.known_inactive[bits[i]]) {
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if (knowledge.known_inactive.at(bits[i])) {
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sig[i] = State::S0;
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did_something = true;
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} else {
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for (auto &it : knowledge.known_active)
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if (GetSize(it) == 1 && it.front() == bits[i]) {
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sig[i] = State::S1;
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did_something = true;
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break;
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}
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} else
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if (knowledge.known_active.at(bits[i])) {
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sig[i] = State::S1;
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did_something = true;
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}
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}
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@ -399,16 +388,14 @@ struct OptMuxtreeWorker
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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for (size_t i = 0; i < knowledge.known_active.size(); i++) {
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if (list_is_subset(knowledge.known_active[i], portinfo.ctrl_sigs)) {
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eval_mux_port(knowledge, mux_idx, port_idx);
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return;
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}
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if (knowledge.known_active.at(portinfo.ctrl_sig)) {
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eval_mux_port(knowledge, mux_idx, port_idx);
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return;
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}
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}
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// compare ports with known_inactive and known_active signals. If all control
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// signals of the port are known_inactive or if the control signals of all other
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// compare ports with known_inactive and known_active signals. If the control
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// signal of the port is known_inactive or if the control signals of all other
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// ports are known_active this port can't be activated. this loop includes the
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// default port but no known_inactive match is performed on the default port.
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size(); port_idx++)
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@ -417,23 +404,17 @@ struct OptMuxtreeWorker
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if (port_idx < muxinfo.ports.size()-1) {
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bool found_non_known_inactive = false;
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for (int i : portinfo.ctrl_sigs)
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if (knowledge.known_inactive[i] == 0)
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found_non_known_inactive = true;
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if (knowledge.known_inactive.at(portinfo.ctrl_sig) == 0)
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found_non_known_inactive = true;
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if (!found_non_known_inactive)
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continue;
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}
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bool port_active = true;
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std::vector<int> other_ctrl_sig;
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for (size_t i = 0; i < muxinfo.ports.size()-1; i++) {
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if (i == port_idx)
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continue;
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other_ctrl_sig.insert(other_ctrl_sig.end(),
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muxinfo.ports[i].ctrl_sigs.begin(), muxinfo.ports[i].ctrl_sigs.end());
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}
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for (size_t i = 0; i < knowledge.known_active.size(); i++) {
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if (list_is_subset(knowledge.known_active[i], other_ctrl_sig))
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if (knowledge.known_active.at(muxinfo.ports[i].ctrl_sig))
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port_active = false;
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}
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if (port_active)
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@ -444,7 +425,10 @@ struct OptMuxtreeWorker
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void eval_root_mux(int mux_idx)
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{
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knowledge_t knowledge;
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knowledge.visited_muxes.insert(mux_idx);
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knowledge.known_inactive.resize(bit2info.size());
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knowledge.known_active.resize(bit2info.size());
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knowledge.visited_muxes.resize(mux2info.size());
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knowledge.visited_muxes[mux_idx] = true;
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eval_mux(knowledge, mux_idx);
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}
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};
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@ -464,7 +448,7 @@ struct OptMuxtreePass : public Pass {
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log("This pass only operates on completely selected modules without processes.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
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extra_args(args, 1, design);
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