mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-25 16:42:35 +00:00
Code Activity

Bump to latest

Browse source
This commit is contained in:
Akash Levy 2025-09-21 01:10:04 -07:00
commit 60d969530b
171 changed files with 2574 additions and 1077 deletions
Download patch file Download diff file Expand all files Collapse all files

10
passes/techmap/abc.cc
View file

@ -375,7 +375,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig)
bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
{
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
FfData ff(&initvals, cell);
gate_type_t type = G(FF);
if (!ff.has_clk)
@ -751,7 +751,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str);
else
log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
log(" %*s %s -> %s\n", int(log_signal(RTLIL::SigSpec(wire)).size()), "",
run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str);
first_line = false;
}
@ -984,7 +984,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
}
if (dff_mode && clk_sig.empty())
log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
log_cmd_error("Clock domain %s not found.\n", clk_str);
const AbcConfig &config = run_abc.config;
if (config.cleanup)
@ -2398,7 +2398,7 @@ struct AbcPass : public Pass {
if (g_arg_from_cmd)
cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g));
else
log_cmd_error("Unsupported gate type: %s", g.c_str());
log_cmd_error("Unsupported gate type: %s", g);
ok_gate:
gate_list.push_back(g);
ok_alias:
@ -2503,7 +2503,7 @@ struct AbcPass : public Pass {
}
}
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

2
passes/techmap/abc9_exe.cc
View file

@ -329,7 +329,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
#endif
if (ret != 0) {
if (check_file_exists(stringf("%s/output.aig", tempdir_name)))
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
else
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
}

95
passes/techmap/abc9_ops.cc
View file

@ -224,7 +224,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
else if (derived_module->get_bool_attribute(ID::abc9_box)) {
for (auto derived_cell : derived_module->cells())
if (derived_cell->is_mem_cell() || RTLIL::builtin_ff_cell_types().count(derived_cell->type)) {
if (derived_cell->is_mem_cell() || derived_cell->is_builtin_ff()) {
derived_module->set_bool_attribute(ID::abc9_box, false);
derived_module->set_bool_attribute(ID::abc9_bypass);
break;
@ -1216,7 +1216,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
if (it != Qi.wire->attributes.end())
it->second.bits()[Qi.offset] = State::Sx;
it->second.set(Qi.offset, State::Sx);
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell);
@ -1526,8 +1526,11 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
log_assert(index < GetSize(A));
int i = 0;
while (i < GetSize(mask)) {
for (int j = 0; j < (1 << index); j++)
std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]);
for (int j = 0; j < (1 << index); j++) {
State bit = mask[i+j];
mask.set(i+j, mask[i+j+(1 << index)]);
mask.set(i+j+(1 << index), bit);
}
i += 1 << (index+1);
}
A[index] = y_bit;
@ -1542,7 +1545,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits()) {
for (auto b : driver_mask) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
@ -1563,6 +1566,70 @@ clone_lut:
design->remove(mapped_mod);
}
static void replace_zbufs(Design *design)
{
design->bufNormalize(true);
std::vector<Cell *> zbufs;
for (auto mod : design->modules()) {
zbufs.clear();
for (auto cell : mod->cells()) {
if (cell->type != ID($buf))
continue;
auto &sig = cell->getPort(ID::A);
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
zbufs.push_back(cell);
break;
}
}
}
for (auto cell : zbufs) {
auto sig = cell->getPort(ID::A);
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
Wire *w = mod->addWire(NEW_ID);
Cell *ud = mod->addCell(NEW_ID, ID($tribuf));
ud->set_bool_attribute(ID(aiger2_zbuf));
ud->setParam(ID::WIDTH, 1);
ud->setPort(ID::Y, w);
ud->setPort(ID::EN, State::S0);
ud->setPort(ID::A, State::S0);
sig[i] = w;
}
}
log("XXX %s -> %s\n", log_signal(cell->getPort(ID::A)), log_signal(sig));
cell->setPort(ID::A, sig);
}
mod->bufNormalize();
}
}
static void restore_zbufs(Design *design)
{
std::vector<Cell *> to_remove;
for (auto mod : design->modules()) {
to_remove.clear();
for (auto cell : mod->cells())
if (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf)))
to_remove.push_back(cell);
for (auto cell : to_remove) {
SigSpec sig_y = cell->getPort(ID::Y);
mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y);
mod->remove(cell);
}
mod->bufNormalize();
}
}
struct Abc9OpsPass : public Pass {
Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
void help() override
@ -1665,6 +1732,8 @@ struct Abc9OpsPass : public Pass {
bool prep_lut_mode = false;
bool prep_box_mode = false;
bool reintegrate_mode = false;
bool replace_zbufs_mode = false;
bool restore_zbufs_mode = false;
bool dff_mode = false;
std::string write_lut_dst;
int maxlut = 0;
@ -1751,16 +1820,30 @@ struct Abc9OpsPass : public Pass {
dff_mode = true;
continue;
}
if (arg == "-replace_zbufs") {
replace_zbufs_mode = true;
valid = true;
continue;
}
if (arg == "-restore_zbufs") {
restore_zbufs_mode = true;
valid = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!valid)
log_cmd_error("At least one of -check, -break_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
log_cmd_error("At least one of -check, -break_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate, -{replace,restore}_zbufs must be specified.\n");
if (dff_mode && !check_mode && !prep_hier_mode && !prep_delays_mode && !prep_xaiger_mode && !reintegrate_mode)
log_cmd_error("'-dff' option is only relevant for -prep_{hier,delay,xaiger} or -reintegrate.\n");
if (replace_zbufs_mode)
replace_zbufs(design);
if (restore_zbufs_mode)
restore_zbufs(design);
if (check_mode)
check(design, dff_mode);
if (prep_hier_mode)

2
passes/techmap/abc_new.cc
View file

@ -169,10 +169,12 @@ struct AbcNewPass : public ScriptPass {
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir));
run(" abc9_ops -replace_zbufs");
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));
run(" abc9_ops -restore_zbufs");
if (!help_mode && mod->has_attribute(ID(abc9_script))) {
if (script_save.empty())

2
passes/techmap/cellmatch.cc
View file

@ -173,7 +173,7 @@ struct CellmatchPass : Pass {
derive_luts = true;
} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
if (!saved_designs.count(args[++argidx]))
log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
log_cmd_error("No design '%s' found!\n", args[argidx]);
lib = saved_designs.at(args[argidx]);
} else {
break;

2
passes/techmap/clockgate.cc
View file

@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
int gated_flop_count = 0;
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(nullptr, cell);

4
passes/techmap/constmap.cc
View file

@ -82,7 +82,7 @@ struct ConstmapPass : public Pass {
}
}
if (!has_port)
log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype.c_str(), cell_portname.c_str());
log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype, cell_portname);
bool has_param = false;
for (auto &p : existing->avail_parameters){
@ -91,7 +91,7 @@ struct ConstmapPass : public Pass {
}
if (!has_param)
log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype.c_str(), cell_paramname.c_str());
log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype, cell_paramname);
}

6
passes/techmap/dffinit.cc
View file

@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
for (int i = 0; i < GetSize(sig); i++) {
if (initval[i] == State::Sx)
continue;
while (GetSize(value) <= i)
value.bits().push_back(State::S0);
if (GetSize(value) <= i)
value.resize(i + 1, State::S0);
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second));
value.bits()[i] = initval[i];
value.set(i, initval[i]);
}
if (highlow_mode && GetSize(value) != 0) {

12
passes/techmap/dfflegalize.cc
View file

@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass {
if (ff.has_arst) {
if (ff.val_arst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_arst.bits()[i] = State::S0;
ff.val_arst.set(i, State::S0);
if (!(supported & (mask << 4)))
ff.val_arst.bits()[i] = State::S1;
ff.val_arst.set(i, State::S1);
}
}
if (ff.has_srst) {
if (ff.val_srst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_srst.bits()[i] = State::S0;
ff.val_srst.set(i, State::S0);
if (!(supported & (mask << 4)))
ff.val_srst.bits()[i] = State::S1;
ff.val_srst.set(i, State::S1);
}
}
}
@ -1196,7 +1196,7 @@ unrecognized:
srst_used.clear();
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);
@ -1208,7 +1208,7 @@ unrecognized:
}
for (auto cell : module->selected_cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);
legalize_ff(ff);

2
passes/techmap/dffunmap.cc
View file

@ -74,7 +74,7 @@ struct DffunmapPass : public Pass {
for (auto cell : mod->selected_cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

2
passes/techmap/extract.cc
View file

@ -605,7 +605,7 @@ struct ExtractPass : public Pass {
f.open(filename.c_str());
if (f.fail()) {
delete map;
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
log_cmd_error("Can't open map file `%s'.\n", filename);
}
Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
f.close();

2
passes/techmap/flowmap.cc
View file

@ -1401,7 +1401,7 @@ struct FlowmapWorker
log_signal(node), log_signal(undef), env.c_str());
}
lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0;
lut_table.set(i, value.as_bool() ? State::S1 : State::S0);
ce.pop();
}

4
passes/techmap/libparse.cc
View file

@ -191,7 +191,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) {
s.next();
lhs = parse(s);
if (s.peek() != ')') {
log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr().c_str());
log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr());
return lhs;
}
s.next();
@ -200,7 +200,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) {
lhs.kind = Kind::NOT;
lhs.children.push_back(parse(s, 7));
} else {
log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr().c_str());
log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr());
return lhs;
}

17
passes/techmap/simplemap.cc
View file

@ -47,7 +47,22 @@ void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
module->connect(RTLIL::SigSig(sig_y, sig_a));
if (sig_a.has_const(State::Sz)) {
SigSpec new_a;
SigSpec new_y;
for (int i = 0; i < GetSize(sig_a); ++i) {
SigBit b = sig_a[i];
if (b == State::Sz)
continue;
new_a.append(b);
new_y.append(sig_y[i]);
}
sig_a = std::move(new_a);
sig_y = std::move(new_y);
}
if (!sig_y.empty())
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)

9
passes/techmap/techmap.cc
View file

@ -690,15 +690,16 @@ struct TechmapWorker
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
RTLIL::Const value;
for (auto &bit : sigmap(conn.second)) {
SigSpec sm = sigmap(conn.second);
RTLIL::Const::Builder builder(GetSize(sm) * bits);
for (auto &bit : sm) {
int val = unique_bit_id.at(bit);
for (int i = 0; i < bits; i++) {
value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0);
builder.push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1;
}
}
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value);
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), builder.build());
}
}

4
passes/techmap/zinit.cc
View file

@ -63,7 +63,7 @@ struct ZinitPass : public Pass {
for (auto cell : module->selected_cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);
@ -76,7 +76,7 @@ struct ZinitPass : public Pass {
if (ff.val_init[i] == State::S1)
bits.insert(i);
else if (ff.val_init[i] != State::S0 && all_mode)
ff.val_init.bits()[i] = State::S0;
ff.val_init.set(i, State::S0);
}
ff.flip_bits(bits);
ff.emit();