mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-29 15:37:59 +00:00
tests: fix some test warnings
This commit is contained in:
parent
ae11156c90
commit
60aa804915
6 changed files with 7 additions and 7 deletions
|
@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
|
|||
endmodule
|
||||
|
||||
module $__SHREG_DFF_P_(input C, D, output Q);
|
||||
parameter DEPTH = 1;
|
||||
parameter DEPTH = 2;
|
||||
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
|
||||
reg [DEPTH-1:0] r = INIT;
|
||||
always @(posedge C)
|
||||
|
@ -38,7 +38,7 @@ endmodule
|
|||
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
|
||||
parameter CLKPOL = 1;
|
||||
parameter ENPOL = 1;
|
||||
parameter DEPTH = 1;
|
||||
parameter DEPTH = 2;
|
||||
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
|
||||
reg [DEPTH-1:0] r = INIT;
|
||||
wire clk = C ^ CLKPOL;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue