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tests: fix some test warnings
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6 changed files with 7 additions and 7 deletions
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@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
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input wire rst;
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input wire [7:0] inp_a;
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input wire [7:0] inp_b;
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output wire [7:0] out;
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output reg [7:0] out;
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always @(posedge clk)
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if (rst) out <= 0;
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