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tests: fix some test warnings
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6 changed files with 7 additions and 7 deletions
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@ -29,7 +29,7 @@ endmodule
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module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
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parameter CLKPOL = 1;
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parameter ENPOL = 1;
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parameter DEPTH = 1;
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parameter DEPTH = 2;
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parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
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reg [DEPTH-1:0] r = INIT;
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wire clk = C ^ CLKPOL;
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