mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-29 07:27:58 +00:00
Code Activity

tests: fix some test warnings

Browse source
This commit is contained in:
Eddie Hung 2020-05-25 10:07:58 -07:00
parent ae11156c90
commit 60aa804915
6 changed files with 7 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/xilinx/pmgen_xilinx_srl.ys
View file

@ -1,6 +1,6 @@
read_verilog -icells <<EOT
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
parameter DEPTH = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;

2
tests/arch/xilinx/xilinx_srl.v
View file

@ -29,7 +29,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;