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Implemented correct handling of signed module parameters

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This commit is contained in:
Clifford Wolf 2013-11-24 17:17:21 +01:00
parent 1e6836933d
commit 609caa23b5
8 changed files with 19 additions and 8 deletions
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8
tests/simple/hierarchy.v
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@ -4,14 +4,20 @@ module top(a, b, y1, y2, y3, y4);
input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;
// this version triggers a bug in icarus verilog
// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
// this version is handled correctly by icarus verilog
submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
endmodule
(* gentb_skip *)
module submod(a, b, y1, y2, y3, y4);
parameter c = 0;
parameter [7:0] d = 0;
input [7:0] a, b;
input [3:0] a, b;
output [7:0] y1, y2, y3, y4;
assign y1 = a;
assign y2 = b;