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Implemented correct handling of signed module parameters

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This commit is contained in:
Clifford Wolf 2013-11-24 17:17:21 +01:00
parent 1e6836933d
commit 609caa23b5
8 changed files with 19 additions and 8 deletions
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2
passes/techmap/techmap.cc
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@ -239,7 +239,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
tpl = techmap_cache[key];
} else {
if (cell->parameters.size() != 0) {
derived_name = tpl->derive(map, parameters);
derived_name = tpl->derive(map, parameters, cell->signed_parameters);
tpl = map->modules[derived_name];
log_continue = true;
}