mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Add RAM32X1D box info

Browse source
This commit is contained in:
Eddie Hung 2019-06-24 22:54:35 -07:00
parent 6f36ec8ecf
commit 6095357390
2 changed files with 12 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

11
techlibs/xilinx/abc_xc7.box
View file

@ -30,16 +30,23 @@ CARRY4 3 1 10 8
592 540 520 356 - 512 548 292 - 228 592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114 580 526 507 398 385 508 528 378 380 114
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
# Outputs: DPO SPO
RAM32X1D 4 0 13 2
- - - - - - 124 124 124 124 124 - -
124 124 124 124 124 - - - - - - - -
# SLICEM/A6LUT # SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO # Outputs: DPO SPO
RAM64X1D 4 0 15 2 RAM64X1D 5 0 15 2
- - - - - - - 642 631 472 407 238 127 - - - - - - - - - 642 631 472 407 238 127 - -
642 631 472 407 238 127 - - - - - - - - - 642 631 472 407 238 127 - - - - - - - - -
# SLICEM/A6LUT + F7[AB]MUX # SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO # Outputs: DPO SPO
RAM128X1D 5 0 17 2 RAM128X1D 6 0 17 2
- - - - - - - - 1009 998 839 774 605 494 450 - - - - - - - - - - 1009 998 839 774 605 494 450 - -
1047 1036 877 812 643 532 478 - - - - - - - - - - 1047 1036 877 812 643 532 478 - - - - - - - - - -

5
techlibs/xilinx/cells_sim.v
View file

@ -281,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule endmodule
(* abc_box_id = 4, abc_scc_break="D" *)
module RAM32X1D ( module RAM32X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
@ -298,7 +299,7 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D; always @(posedge clk) if (WE) mem[a] <= D;
endmodule endmodule
(* abc_box_id = 4, abc_scc_break="D" *) (* abc_box_id = 5, abc_scc_break="D" *)
module RAM64X1D ( module RAM64X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
@ -316,7 +317,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D; always @(posedge clk) if (WE) mem[a] <= D;
endmodule endmodule
(* abc_box_id = 5, abc_scc_break="D" *) (* abc_box_id = 6, abc_scc_break="D" *)
module RAM128X1D ( module RAM128X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,