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Add memory_bmux2rom pass.

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Marcelina Kościelnicka 2022-05-18 21:20:42 +02:00
parent 982a11c709
commit 606f1637ae
4 changed files with 124 additions and 1 deletions
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1
passes/memory/Makefile.inc
View file

@ -10,5 +10,6 @@ OBJS += passes/memory/memory_memx.o
OBJS += passes/memory/memory_nordff.o
OBJS += passes/memory/memory_narrow.o
OBJS += passes/memory/memory_libmap.o
OBJS += passes/memory/memory_bmux2rom.o
OBJS += passes/memory/memlib.o

10
passes/memory/memory.cc
View file

@ -31,13 +31,14 @@ struct MemoryPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" memory [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-bram <bram_rules>] [selection]\n");
log(" memory [-norom] [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-bram <bram_rules>] [selection]\n");
log("\n");
log("This pass calls all the other memory_* passes in a useful order:\n");
log("\n");
log(" opt_mem\n");
log(" opt_mem_priority\n");
log(" opt_mem_feedback\n");
log(" memory_bmux2rom (skipped if called with -norom)\n");
log(" memory_dff (skipped if called with -nordff or -memx)\n");
log(" opt_clean\n");
log(" memory_share [-nowiden] [-nosat]\n");
@ -54,6 +55,7 @@ struct MemoryPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_norom = false;
bool flag_nomap = false;
bool flag_nordff = false;
bool flag_memx = false;
@ -65,6 +67,10 @@ struct MemoryPass : public Pass {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-norom") {
flag_norom = true;
continue;
}
if (args[argidx] == "-nomap") {
flag_nomap = true;
continue;
@ -97,6 +103,8 @@ struct MemoryPass : public Pass {
Pass::call(design, "opt_mem");
Pass::call(design, "opt_mem_priority");
Pass::call(design, "opt_mem_feedback");
if (!flag_norom)
Pass::call(design, "memory_bmux2rom");
if (!flag_nordff)
Pass::call(design, "memory_dff");
Pass::call(design, "opt_clean");

87
passes/memory/memory_bmux2rom.cc Normal file
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@ -0,0 +1,87 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2022 Marcelina Kościelnicka <mwk@0x04.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/mem.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct MemoryBmux2RomPass : public Pass {
MemoryBmux2RomPass() : Pass("memory_bmux2rom", "convert muxes to ROMs") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" memory_bmux2rom [options] [selection]\n");
log("\n");
log("This pass converts $bmux cells with constant A input to ROMs.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) {
for (auto cell : module->selected_cells()) {
if (cell->type != ID($bmux))
continue;
SigSpec sig_a = cell->getPort(ID::A);
if (!sig_a.is_fully_const())
continue;
int abits = cell->getParam(ID::S_WIDTH).as_int();
int width = cell->getParam(ID::WIDTH).as_int();
if (abits < 3)
continue;
// Ok, let's do it.
Mem mem(module, NEW_ID, width, 0, 1 << abits);
mem.attributes = cell->attributes;
MemInit init;
init.addr = 0;
init.data = sig_a.as_const();
init.en = Const(State::S1, width);
mem.inits.push_back(std::move(init));
MemRd rd;
rd.addr = cell->getPort(ID::S);
rd.data = cell->getPort(ID::Y);
rd.init_value = Const(State::Sx, width);
rd.arst_value = Const(State::Sx, width);
rd.srst_value = Const(State::Sx, width);
mem.rd_ports.push_back(std::move(rd));
mem.emit();
module->remove(cell);
}
}
}
} MemoryBmux2RomPass;
PRIVATE_NAMESPACE_END

27
tests/opt/memory_bmux2rom.ys Normal file
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@ -0,0 +1,27 @@
read_ilang << EOT
module \top
wire width 4 input 0 \S
wire width 5 output 1 \Y
cell $bmux $0
parameter \WIDTH 5
parameter \S_WIDTH 4
connect \A 80'10110100011101110001110010001110101010111000110011111111111110100000110100111000
connect \S \S
connect \Y \Y
end
end
EOT
hierarchy -auto-top
design -save preopt
memory_bmux2rom
select -assert-count 1 t:$memrd_v2
memory_map
opt_dff
design -stash postopt
equiv_opt -assert -run prepare: dummy