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bugfix in blif front-end

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This commit is contained in:
Clifford Wolf 2015-05-18 11:15:49 +02:00
parent 83499dc1ba
commit 6061b7bd58
2 changed files with 6 additions and 6 deletions
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6
frontends/blif/blifparse.cc
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@ -207,10 +207,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name)
RTLIL::SigSpec input_sig, output_sig; RTLIL::SigSpec input_sig, output_sig;
while ((p = strtok(NULL, " \t\r\n")) != NULL) { while ((p = strtok(NULL, " \t\r\n")) != NULL) {
RTLIL::Wire *wire; RTLIL::Wire *wire;
if (module->wires_.count(stringf("\\%s", p)) > 0) { if (module->wires_.count(RTLIL::escape_id(p)) > 0) {
wire = module->wires_.at(stringf("\\%s", p)); wire = module->wires_.at(RTLIL::escape_id(p));
} else { } else {
wire = module->addWire(stringf("\\%s", p)); wire = module->addWire(RTLIL::escape_id(p));
} }
input_sig.append(wire); input_sig.append(wire);
} }

6
tests/vloghtb/test_febe.sh
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@ -6,8 +6,8 @@ source common.sh
f=$1 f=$1
n=$(basename ${f%.v}) n=$(basename ${f%.v})
test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f
test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f
test_febe blif "synth; splitnets -ports" ".blif" "write_blif -icells" "read_blif" "-ignore_div_by_zero" $n $f test_febe blif "synth; splitnets -ports" ".blif" "write_blif" "read_blif" "-ignore_div_by_zero" $n $f
exit 0 exit 0