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https://github.com/YosysHQ/yosys
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fix for python 2.6.6
This commit is contained in:
Clifford Wolf
parent
aed4d763cf
commit
604c097f98
3 changed files with 172 additions and 165 deletions
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@ -34,76 +34,78 @@ def random_expr(variables):
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raise AssertionError
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raise AssertionError
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for idx in range(50):
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for idx in range(50):
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with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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with file('temp/uut_%05d.v' % idx, 'w') as f:
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rst2 = random.choice([False, True])
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with redirect_stdout(f):
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if rst2:
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rst2 = random.choice([False, True])
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print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx))
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if rst2:
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print(' input clk, rst1, rst2;')
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print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx))
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print(' output rst;')
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print(' input clk, rst1, rst2;')
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print(' assign rst = rst1 || rst2;')
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print(' output rst;')
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else:
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print(' assign rst = rst1 || rst2;')
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print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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else:
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print(' input clk, rst;')
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print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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variables=['a', 'b', 'c', 'x', 'y', 'z']
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print(' input clk, rst;')
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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variables=['a', 'b', 'c', 'x', 'y', 'z']
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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state_bits = random.randint(5, 16);
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print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)',
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state_bits = random.randint(5, 16);
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'(* fsm_encoding = "binary" *)']), state_bits-1))
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print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)',
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states=[]
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'(* fsm_encoding = "binary" *)']), state_bits-1))
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for i in range(random.randint(2, 10)):
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states=[]
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n = random.randint(0, 2**state_bits-1)
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for i in range(random.randint(2, 10)):
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if n not in states:
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n = random.randint(0, 2**state_bits-1)
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states.append(n)
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if n not in states:
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print(' always @(posedge clk) begin')
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states.append(n)
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print(' if (%s) begin' % ('rst1' if rst2 else 'rst'))
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print(' always @(posedge clk) begin')
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print(' x <= %d;' % random.randint(0, 2**31-1))
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print(' if (%s) begin' % ('rst1' if rst2 else 'rst'))
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print(' y <= %d;' % random.randint(0, 2**31-1))
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print(' x <= %d;' % random.randint(0, 2**31-1))
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print(' z <= %d;' % random.randint(0, 2**31-1))
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print(' y <= %d;' % random.randint(0, 2**31-1))
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print(' state <= %d;' % random.choice(states))
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print(' z <= %d;' % random.randint(0, 2**31-1))
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print(' end else begin')
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print(' state <= %d;' % random.choice(states))
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print(' case (state)')
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print(' end else begin')
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for state in states:
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print(' case (state)')
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print(' %d: begin' % state)
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for state in states:
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for var in ('x', 'y', 'z'):
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print(' %d: begin' % state)
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print(' %s <= %s;' % (var, random_expr(variables)))
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for var in ('x', 'y', 'z'):
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next_states = states[:]
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print(' %s <= %s;' % (var, random_expr(variables)))
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for i in range(random.randint(0, len(states))):
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next_states = states[:]
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next_state = random.choice(next_states)
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for i in range(random.randint(0, len(states))):
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next_states.remove(next_state)
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next_state = random.choice(next_states)
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print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables),
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next_states.remove(next_state)
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random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state))
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print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables),
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print(' end')
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random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state))
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print(' endcase')
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print(' end')
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if rst2:
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print(' endcase')
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print(' if (rst2) begin')
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if rst2:
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print(' x <= a;')
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print(' if (rst2) begin')
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print(' y <= b;')
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print(' x <= a;')
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print(' z <= c;')
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print(' y <= b;')
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print(' state <= %d;' % random.choice(states))
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print(' z <= c;')
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print(' end')
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print(' state <= %d;' % random.choice(states))
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print(' end')
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print(' end')
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print(' end')
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print(' end')
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print('endmodule')
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print(' end')
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with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
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print('endmodule')
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if test_verific:
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with file('temp/uut_%05d.ys' % idx, 'w') as f:
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print('read_verilog temp/uut_%05d.v' % idx)
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with redirect_stdout(f):
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print('proc;; rename uut_%05d gold' % idx)
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if test_verific:
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print('verific -vlog2k temp/uut_%05d.v' % idx)
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print('read_verilog temp/uut_%05d.v' % idx)
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print('verific -import uut_%05d' % idx)
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print('proc;; rename uut_%05d gold' % idx)
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print('rename uut_%05d gate' % idx)
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print('verific -vlog2k temp/uut_%05d.v' % idx)
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else:
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print('verific -import uut_%05d' % idx)
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print('read_verilog temp/uut_%05d.v' % idx)
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print('rename uut_%05d gate' % idx)
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print('proc;;')
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else:
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print('copy uut_%05d gold' % idx)
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print('read_verilog temp/uut_%05d.v' % idx)
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print('rename uut_%05d gate' % idx)
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print('proc;;')
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print('cd gate')
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print('copy uut_%05d gold' % idx)
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print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
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print('rename uut_%05d gate' % idx)
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print('cd ..')
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print('cd gate')
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print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
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print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
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print('cd ..')
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print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
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@ -40,52 +40,55 @@ def random_expression(depth = 3, maxparam = 0):
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raise
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raise
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for idx in range(100):
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for idx in range(100):
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with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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with file('temp/uut_%05d.v' % idx, 'w') as f:
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print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
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with redirect_stdout(f):
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for i in range(30):
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print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
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if idx < 10:
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for i in range(30):
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print('localparam p%02d = %s;' % (i, random_expression()))
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if idx < 10:
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else:
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print('localparam p%02d = %s;' % (i, random_expression()))
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print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression()))
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else:
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for i in range(30, 60):
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print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression()))
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if idx < 10:
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for i in range(30, 60):
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print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30)))
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if idx < 10:
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else:
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print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30)))
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print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30)))
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else:
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for i in range(100):
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print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30)))
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print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60)))
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for i in range(100):
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print('endmodule')
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print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60)))
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with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
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print('endmodule')
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print('read_verilog uut_%05d.v' % idx)
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with file('temp/uut_%05d.ys' % idx, 'w') as f:
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print('rename uut_%05d uut_%05d_syn' % (idx, idx))
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with redirect_stdout(f):
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print('write_verilog uut_%05d_syn.v' % idx)
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print('read_verilog uut_%05d.v' % idx)
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with file('temp/uut_%05d_tb.v' % idx, 'w') as f, redirect_stdout(f):
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print('rename uut_%05d uut_%05d_syn' % (idx, idx))
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print('module uut_%05d_tb;\n' % idx)
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print('write_verilog uut_%05d_syn.v' % idx)
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print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)])))
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with file('temp/uut_%05d_tb.v' % idx, 'w') as f:
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print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)])))
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with redirect_stdout(f):
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print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)])))
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print('module uut_%05d_tb;\n' % idx)
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print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)])))
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print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)])))
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print('task compare_ref_syn;')
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print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)])))
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print(' input [7:0] i;')
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print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)])))
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print(' input [63:0] r, s;')
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print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)])))
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print(' reg [64*8-1:0] buffer;')
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print('task compare_ref_syn;')
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print(' integer j;')
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print(' input [7:0] i;')
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print(' begin')
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print(' input [63:0] r, s;')
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print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin')
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print(' reg [64*8-1:0] buffer;')
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print(' // $display("%d: %b %b", i, r, s);')
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print(' integer j;')
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print(' end else if (r === s) begin ')
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print(' begin')
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print(' // $display("%d: %b %b", i, r, s);')
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print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin')
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print(' end else begin ')
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print(' // $display("%d: %b %b", i, r, s);')
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print(' for (j = 0; j < 64; j = j+1)')
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print(' end else if (r === s) begin ')
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print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";')
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print(' // $display("%d: %b %b", i, r, s);')
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print(' $display("\\n%3d: %b %b", i, r, s);')
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print(' end else begin ')
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print(' $display(" %s %s", buffer, buffer);')
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print(' for (j = 0; j < 64; j = j+1)')
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print(' end')
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print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";')
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print(' end')
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print(' $display("\\n%3d: %b %b", i, r, s);')
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print('endtask')
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print(' $display(" %s %s", buffer, buffer);')
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print('initial begin #1;')
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print(' end')
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for i in range(100):
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print(' end')
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print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i))
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print('endtask')
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print('end')
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print('initial begin #1;')
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print('endmodule')
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for i in range(100):
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print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i))
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print('end')
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print('endmodule')
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@ -25,49 +25,51 @@ def maybe_plus_x(expr):
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return expr
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return expr
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for idx in range(100):
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for idx in range(100):
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with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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with file('temp/uut_%05d.v' % idx, 'w') as f:
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if random.choice(['bin', 'uni']) == 'bin':
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with redirect_stdout(f):
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print('module uut_%05d(a, b, c, d, x, s, y);' % (idx))
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if random.choice(['bin', 'uni']) == 'bin':
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op = random.choice([
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print('module uut_%05d(a, b, c, d, x, s, y);' % (idx))
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random.choice(['+', '-', '*', '/', '%']),
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op = random.choice([
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random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]),
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random.choice(['+', '-', '*', '/', '%']),
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random.choice(['<<', '>>', '<<<', '>>>']),
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random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]),
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random.choice(['|', '&', '^', '~^', '||', '&&']),
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random.choice(['<<', '>>', '<<<', '>>>']),
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])
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random.choice(['|', '&', '^', '~^', '||', '&&']),
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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])
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input s;')
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print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' output [%d:0] y;' % random.randint(0, 8))
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print(' input s;')
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print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' %
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print(' output [%d:0] y;' % random.randint(0, 8))
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(random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'),
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print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' %
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random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'),
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(random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'),
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random_plus_x() if random.randint(0, 4) == 0 else ''))
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random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'),
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print('endmodule')
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random_plus_x() if random.randint(0, 4) == 0 else ''))
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else:
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print('endmodule')
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print('module uut_%05d(a, b, x, s, y);' % (idx))
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else:
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op = random.choice(['~', '-', '!'])
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print('module uut_%05d(a, b, x, s, y);' % (idx))
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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op = random.choice(['~', '-', '!'])
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input s;')
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print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' output [%d:0] y;' % random.randint(0, 8))
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print(' input s;')
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print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' %
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print(' output [%d:0] y;' % random.randint(0, 8))
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(random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'),
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print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' %
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random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'),
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(random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'),
|
||||||
random_plus_x() if random.randint(0, 4) == 0 else ''))
|
random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'),
|
||||||
print('endmodule')
|
random_plus_x() if random.randint(0, 4) == 0 else ''))
|
||||||
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
|
print('endmodule')
|
||||||
print('read_verilog temp/uut_%05d.v' % idx)
|
with file('temp/uut_%05d.ys' % idx, 'w') as f:
|
||||||
print('proc;;')
|
with redirect_stdout(f):
|
||||||
print('copy uut_%05d gold' % idx)
|
print('read_verilog temp/uut_%05d.v' % idx)
|
||||||
print('rename uut_%05d gate' % idx)
|
print('proc;;')
|
||||||
print('tee -a temp/all_share_log.txt log')
|
print('copy uut_%05d gold' % idx)
|
||||||
print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx)
|
print('rename uut_%05d gate' % idx)
|
||||||
print('tee -a temp/all_share_log.txt wreduce')
|
print('tee -a temp/all_share_log.txt log')
|
||||||
print('tee -a temp/all_share_log.txt share -aggressive gate')
|
print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx)
|
||||||
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
|
print('tee -a temp/all_share_log.txt wreduce')
|
||||||
print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter')
|
print('tee -a temp/all_share_log.txt share -aggressive gate')
|
||||||
|
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
|
||||||
|
print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter')
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue