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https://github.com/YosysHQ/yosys
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fix for python 2.6.6
This commit is contained in:
Clifford Wolf
parent
aed4d763cf
commit
604c097f98
3 changed files with 172 additions and 165 deletions
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@ -34,76 +34,78 @@ def random_expr(variables):
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raise AssertionError
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for idx in range(50):
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with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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rst2 = random.choice([False, True])
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if rst2:
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print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst1, rst2;')
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print(' output rst;')
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print(' assign rst = rst1 || rst2;')
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else:
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print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst;')
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variables=['a', 'b', 'c', 'x', 'y', 'z']
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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state_bits = random.randint(5, 16);
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print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)',
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'(* fsm_encoding = "binary" *)']), state_bits-1))
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states=[]
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for i in range(random.randint(2, 10)):
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n = random.randint(0, 2**state_bits-1)
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if n not in states:
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states.append(n)
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print(' always @(posedge clk) begin')
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print(' if (%s) begin' % ('rst1' if rst2 else 'rst'))
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print(' x <= %d;' % random.randint(0, 2**31-1))
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print(' y <= %d;' % random.randint(0, 2**31-1))
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print(' z <= %d;' % random.randint(0, 2**31-1))
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print(' state <= %d;' % random.choice(states))
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print(' end else begin')
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print(' case (state)')
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for state in states:
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print(' %d: begin' % state)
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for var in ('x', 'y', 'z'):
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print(' %s <= %s;' % (var, random_expr(variables)))
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next_states = states[:]
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for i in range(random.randint(0, len(states))):
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next_state = random.choice(next_states)
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next_states.remove(next_state)
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print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables),
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random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state))
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print(' end')
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print(' endcase')
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if rst2:
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print(' if (rst2) begin')
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print(' x <= a;')
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print(' y <= b;')
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print(' z <= c;')
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print(' state <= %d;' % random.choice(states))
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print(' end')
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print(' end')
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print(' end')
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print('endmodule')
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with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
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if test_verific:
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print('read_verilog temp/uut_%05d.v' % idx)
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print('proc;; rename uut_%05d gold' % idx)
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print('verific -vlog2k temp/uut_%05d.v' % idx)
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print('verific -import uut_%05d' % idx)
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print('rename uut_%05d gate' % idx)
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else:
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print('read_verilog temp/uut_%05d.v' % idx)
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print('proc;;')
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print('copy uut_%05d gold' % idx)
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print('rename uut_%05d gate' % idx)
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print('cd gate')
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print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
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print('cd ..')
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print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
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with file('temp/uut_%05d.v' % idx, 'w') as f:
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with redirect_stdout(f):
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rst2 = random.choice([False, True])
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if rst2:
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print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst1, rst2;')
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print(' output rst;')
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print(' assign rst = rst1 || rst2;')
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else:
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print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst;')
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variables=['a', 'b', 'c', 'x', 'y', 'z']
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31)))
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state_bits = random.randint(5, 16);
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print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)',
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'(* fsm_encoding = "binary" *)']), state_bits-1))
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states=[]
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for i in range(random.randint(2, 10)):
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n = random.randint(0, 2**state_bits-1)
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if n not in states:
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states.append(n)
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print(' always @(posedge clk) begin')
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print(' if (%s) begin' % ('rst1' if rst2 else 'rst'))
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print(' x <= %d;' % random.randint(0, 2**31-1))
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print(' y <= %d;' % random.randint(0, 2**31-1))
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print(' z <= %d;' % random.randint(0, 2**31-1))
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print(' state <= %d;' % random.choice(states))
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print(' end else begin')
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print(' case (state)')
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for state in states:
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print(' %d: begin' % state)
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for var in ('x', 'y', 'z'):
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print(' %s <= %s;' % (var, random_expr(variables)))
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next_states = states[:]
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for i in range(random.randint(0, len(states))):
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next_state = random.choice(next_states)
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next_states.remove(next_state)
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print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables),
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random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state))
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print(' end')
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print(' endcase')
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if rst2:
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print(' if (rst2) begin')
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print(' x <= a;')
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print(' y <= b;')
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print(' z <= c;')
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print(' state <= %d;' % random.choice(states))
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print(' end')
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print(' end')
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print(' end')
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print('endmodule')
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with file('temp/uut_%05d.ys' % idx, 'w') as f:
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with redirect_stdout(f):
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if test_verific:
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print('read_verilog temp/uut_%05d.v' % idx)
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print('proc;; rename uut_%05d gold' % idx)
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print('verific -vlog2k temp/uut_%05d.v' % idx)
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print('verific -import uut_%05d' % idx)
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print('rename uut_%05d gate' % idx)
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else:
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print('read_verilog temp/uut_%05d.v' % idx)
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print('proc;;')
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print('copy uut_%05d gold' % idx)
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print('rename uut_%05d gate' % idx)
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print('cd gate')
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print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
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print('cd ..')
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print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
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