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https://github.com/YosysHQ/yosys
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abstract: -value MVP, use buffer-normalized mode
This commit is contained in:
Emil J. Tywoniak
parent
4637fa74e3
commit
6027030215
2 changed files with 121 additions and 62 deletions
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@ -57,70 +57,70 @@ bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
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return true;
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}
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bool abstract_value(Module* mod, Wire* wire, Wire* enable, bool enable_pol) {
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// (void)mod->addMux(NEW_ID,
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// mux_a,
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// mux_b,
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// enable,
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// abstracted);
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// cell->setPort(ID::D, SigSpec(abstracted));
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return false;
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}
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struct AbstractInitCtx {
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struct AbstractPortCtx {
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Module* mod;
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SigMap sigmap;
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pool<SigBit> init_bits;
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pool<std::pair<Cell*, IdString>> outs;
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};
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void collect_init_bits_cells(AbstractInitCtx& ctx) {
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// TODO Should this discriminate between FFs and other cells?
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for (auto cell : ctx.mod->selected_cells()) {
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// Add all sigbits on all cell outputs to init_bits
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for (auto &conn : cell->connections()) {
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if (cell->output(conn.first)) {
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for (auto bit : conn.second) {
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log_debug("init: cell %s output %s\n", cell->name.c_str(), log_signal(bit));
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ctx.init_bits.insert(ctx.sigmap(bit));
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}
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}
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void collect_selected_ports(AbstractPortCtx& ctx) {
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for (Cell* cell : ctx.mod->cells()) {
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for (auto& conn : cell->connections()) {
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// we bufnorm
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log_assert(conn.second.is_wire() || conn.second.is_fully_const());
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if (conn.second.is_wire() && cell->output(conn.first))
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if (ctx.mod->selected(cell) || ctx.mod->selected(conn.second.as_wire()))
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ctx.outs.insert(std::make_pair(cell, conn.first));
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}
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}
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}
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void collect_init_bits_wires(AbstractInitCtx& ctx) {
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for (auto wire : ctx.mod->selected_wires()) {
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auto canonical = ctx.sigmap(wire);
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// Find canonical drivers of all the wire bits and add them to init_bits
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for (auto bit : canonical.bits()) {
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log_debug("init: wire %s bit %s\n", wire->name.c_str(), log_signal(bit));
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ctx.init_bits.insert(ctx.sigmap(bit));
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unsigned int abstract_value(Module* mod, Wire* enable, bool enable_pol) {
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AbstractPortCtx ctx {mod, SigMap(mod), {}};
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collect_selected_ports(ctx);
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unsigned int changed = 0;
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for (auto [cell, port] : ctx.outs) {
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SigSpec sig = cell->getPort(port);
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log_assert(sig.is_wire());
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Wire* original = mod->addWire(NEW_ID, sig.size());
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cell->setPort(port, original);
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auto anyseq = mod->Anyseq(NEW_ID, sig.size());
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// This code differs from abstract_state
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// in that we reuse the original signal as the mux output,
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// not input
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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mux_a = original;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = original;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable,
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sig);
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changed++;
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}
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return changed;
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}
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unsigned int abstract_init(Module* mod) {
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AbstractInitCtx ctx {mod, SigMap(mod), pool<SigBit>()};
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pool<SigBit> init_bits;
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collect_init_bits_cells(ctx);
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collect_init_bits_wires(ctx);
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AbstractPortCtx ctx {mod, SigMap(mod), {}};
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collect_selected_ports(ctx);
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unsigned int changed = 0;
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for (SigBit bit : ctx.init_bits) {
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next_sigbit:
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if (!bit.is_wire() || !bit.wire->has_attribute(ID::init))
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for (auto [cell, port] : ctx.outs) {
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SigSpec sig = cell->getPort(port);
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log_assert(sig.is_wire());
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if (!sig.as_wire()->has_attribute(ID::init))
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continue;
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Const init = bit.wire->attributes.at(ID::init);
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std::vector<RTLIL::State>& bits = init.bits();
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bits[bit.offset] = RTLIL::State::Sx;
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changed++;
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for (auto bit : bits)
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if (bit != RTLIL::State::Sx)
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goto next_sigbit;
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// All bits are Sx, erase init attribute entirely
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bit.wire->attributes.erase(ID::init);
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Const init = sig.as_wire()->attributes.at(ID::init);
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sig.as_wire()->attributes.erase(ID::init);
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changed += sig.size();
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}
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return changed;
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}
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@ -174,6 +174,7 @@ struct AbstractPass : public Pass {
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}
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extra_args(args, argidx, design);
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design->bufNormalize(true);
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unsigned int changed = 0;
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if ((mode == State) || (mode == Value)) {
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if (!enable_name.length())
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@ -191,14 +192,13 @@ struct AbstractPass : public Pass {
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if (ct.cell_types.count(cell->type))
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changed += abstract_state(mod, cell, enable_wire, enable_pol);
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} else {
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// Value
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for (auto wire : mod->selected_wires()) {
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changed += abstract_value(mod, wire, enable_wire, enable_pol);
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}
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log_cmd_error("Unsupported (TODO)\n");
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changed += abstract_value(mod, enable_wire, enable_pol);
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}
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}
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log("Abstracted %d cells.\n", changed);
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if (mode == State)
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log("Abstracted %d cells.\n", changed);
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else
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log("Abstracted %d values.\n", changed);
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} else if (mode == Initial) {
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for (auto mod : design->selected_modules()) {
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changed += abstract_init(mod);
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@ -207,6 +207,7 @@ struct AbstractPass : public Pass {
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} else {
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log_cmd_error("No mode selected, see help message\n");
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}
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design->bufNormalize(false);
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}
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} AbstractPass;
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@ -1,9 +1,9 @@
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read_verilog <<EOT
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module half_clock (CLK, Q);
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module half_clock (CLK, Q, magic);
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input CLK;
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output reg Q;
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reg magic;
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input magic;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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@ -12,16 +12,16 @@ EOT
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proc
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# show -prefix before_base
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abstract -state -enablen magic
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check
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check -assert
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# show -prefix after_base
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design -reset
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read_verilog <<EOT
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module half_clock_en (CLK, E, Q);
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module half_clock_en (CLK, E, Q, magic);
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input CLK;
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input E;
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output reg Q;
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reg magic;
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input magic;
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always @(posedge CLK)
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if (E)
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Q <= ~Q;
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@ -33,7 +33,7 @@ opt_expr
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opt_dff
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# show -prefix before_en
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abstract -state -enablen magic
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check
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check -assert
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# show -prefix after_en
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design -reset
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@ -50,9 +50,35 @@ proc
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opt_expr
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opt_dff
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dump
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select -none
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abstract -init
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check
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select -clear
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check -assert
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# dump
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design -reset
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read_verilog <<EOT
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module main (input [3:0] baz);
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reg foo;
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reg bar;
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assign foo = bar;
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assign bar = baz[0];
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reg aaa = 1'b1;
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always @(posedge bar)
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aaa <= ~aaa;
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endmodule
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EOT
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proc -noopt
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# show -prefix before_init
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dump
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select -none
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abstract -init
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select -clear
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# show -prefix after_init
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dump
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check -assert
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# dump
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design -reset
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@ -85,6 +111,38 @@ opt_expr
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opt_dff
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# show -prefix before_a
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abstract -state -enablen magic
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check
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check -assert
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# show -prefix after_a
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# opt_clean
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# opt_clean
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design -reset
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read_verilog <<EOT
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module this_adff (CLK, ARST, D, Q, magic);
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parameter WIDTH = 2;
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parameter CLK_POLARITY = 1'b1;
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parameter ARST_POLARITY = 1'b1;
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parameter ARST_VALUE = 0;
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input CLK, ARST, magic;
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input [WIDTH-1:0] D;
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output reg [WIDTH-1:0] Q;
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wire pos_clk = CLK == CLK_POLARITY;
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wire pos_arst = ARST == ARST_POLARITY;
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always @(posedge pos_clk, posedge pos_arst) begin
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if (pos_arst)
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Q <= ARST_VALUE;
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else
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Q <= D;
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end
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endmodule
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EOT
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proc
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# show -prefix before_value
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abstract -value -enablen magic
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check -assert
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clean
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# show -prefix after_value
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# dump
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