From e0152319f5ed6d99eb38bf6da40157a60fd48e04 Mon Sep 17 00:00:00 2001
From: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Date: Sun, 4 Dec 2016 11:28:25 -0200
Subject: [PATCH 01/35] Added required structure to implement unit tests

Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.

Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
---
 .gitignore                     |  3 +++
 Makefile                       | 14 ++++++++++++++
 tests/unit/Makefile            | 28 ++++++++++++++++++++++++++++
 tests/unit/kernel/logTest.cc   | 14 ++++++++++++++
 tests/unit/kernel/rtlilTest.cc | 14 ++++++++++++++
 5 files changed, 73 insertions(+)
 create mode 100644 tests/unit/Makefile
 create mode 100644 tests/unit/kernel/logTest.cc
 create mode 100644 tests/unit/kernel/rtlilTest.cc

diff --git a/.gitignore b/.gitignore
index 93e28cd6c..cd624f233 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,7 @@
 *.o
 *.d
 .*.swp
+*.gch
 /.cproject
 /.project
 /.settings
@@ -27,3 +28,5 @@
 /yosys-win32-vcxsrc-*
 /yosysjs-*
 /libyosys.so
+/tests/unit/bintest/
+/tests/unit/objtest/
diff --git a/Makefile b/Makefile
index 9bf67d349..340fe1229 100644
--- a/Makefile
+++ b/Makefile
@@ -45,6 +45,9 @@ TARGETS = yosys$(EXE) yosys-config
 PRETTY = 1
 SMALL = 0
 
+# Unit test
+UNITESTPATH := tests/unit
+
 all: top-all
 
 YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
@@ -447,6 +450,17 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Passed \"make vloghtb\"."
 	@echo ""
 
+# Unit test
+unit-test: libyosys.so
+	@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
+		CXXFLAGS="$(CXXFLAGS)" LDLIBS="$(LDLIBS)" ROOTPATH="$(CURDIR)"
+
+run-all-unitest:
+	@$(MAKE) -C $(UNITESTPATH) run-tests
+
+clean-unit-test:
+	@$(MAKE) -C $(UNITESTPATH) clean
+
 install: $(TARGETS) $(EXTRA_TARGETS)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR)
 	$(INSTALL_SUDO) install $(TARGETS) $(DESTDIR)$(BINDIR)
diff --git a/tests/unit/Makefile b/tests/unit/Makefile
new file mode 100644
index 000000000..16f65ec20
--- /dev/null
+++ b/tests/unit/Makefile
@@ -0,0 +1,28 @@
+GTESTFLAG := -lgtest -lgtest_main
+RPATH := -Wl,-rpath
+EXTRAFLAGS := -lyosys
+
+ALLTESTFILE := $(wildcard ./**/*Test.cc)
+OBJTEST := objtest
+BINTEST := bintest
+
+all: prepare $(ALLTESTFILE:%Test.cc=%Test.o)
+
+%Test.o: %Test.cc
+	$(CXX) -o $(OBJTEST)/$(notdir $@) -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $<
+	$(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) -o \
+		$(BINTEST)/$(basename $(notdir $@)) $(OBJTEST)/$(notdir $@) $(LDLIBS) \
+		$(GTESTFLAG) $(EXTRAFLAGS)
+	
+.PHONY: prepare run-tests clean
+
+run-tests:
+	$(CURDIR)/$(BINTEST)/*
+
+prepare:
+	mkdir -p $(OBJTEST)
+	mkdir -p $(BINTEST)
+
+clean:
+	rm -rf $(OBJTEST)
+	rm -rf $(BINTEST)
diff --git a/tests/unit/kernel/logTest.cc b/tests/unit/kernel/logTest.cc
new file mode 100644
index 000000000..62b4f3b98
--- /dev/null
+++ b/tests/unit/kernel/logTest.cc
@@ -0,0 +1,14 @@
+#include <gtest/gtest.h>
+
+#include "kernel/yosys.h"
+#include "kernel/log.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+TEST(KernelLogTest, logvValidValues)
+{
+	//TODO: Implement log test
+	EXPECT_EQ(7, 7);
+}
+
+YOSYS_NAMESPACE_END
diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc
new file mode 100644
index 000000000..d9eeed555
--- /dev/null
+++ b/tests/unit/kernel/rtlilTest.cc
@@ -0,0 +1,14 @@
+#include <gtest/gtest.h>
+
+#include "kernel/yosys.h"
+#include "kernel/rtlil.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+TEST(KernelRtlilTest, getReferenceValid)
+{
+	//TODO: Implement rtlil test
+	EXPECT_EQ(33, 33);
+}
+
+YOSYS_NAMESPACE_END

From 3f2f64f41475550527a5621f57d0b0d2b30ee179 Mon Sep 17 00:00:00 2001
From: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Date: Sun, 4 Dec 2016 11:35:13 -0200
Subject: [PATCH 02/35] Added explanation about configure and create test

Added explanation about configure unit test environment and how to add new unit tests
---
 CodingReadme | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/CodingReadme b/CodingReadme
index cbe1fb8be..d2e975dab 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -411,3 +411,78 @@ Updating the website:
 	git commit -am update
 	make push
 
+How to add unit test
+====================
+
+Unit test brings some advantages, briefly, we can list some of them (reference
+[1](https://en.wikipedia.org/wiki/Unit_testing)):
+
+* Tests reduce bugs in new features;
+* Tests reduce bugs in existing features;
+* Tests are good documentation;
+* Tests reduce the cost of change;
+* Tests allow refactoring;
+
+With those advantages in mind, it was required to choose a framework which fits
+well with C/C++ code.  Hence, it was chosen (google test)
+[https://github.com/google/googletest], because it is largely used and it is
+relatively easy learn.
+
+Install and configure google test (manually)
+============================================
+
+In this section, you will see a brief description of how to install google
+test. However, it is strongly recommended that you take a look to the official
+repository (https://github.com/google/googletest) and refers to that if you
+have any problem to install it. Follow the steps below:
+
+* Install: cmake
+* Clone google test project from: //github.com/rodrigosiqueira/logbook.git and
+  enter in the project directory
+* Inside project directory, type:
+
+```
+cmake -DBUILD_SHARED_LIBS=ON .
+make
+```
+
+* After compilation, copy all "*.so" inside directory "googlemock" and
+  "googlemock/gtest" to "/usr/lib/"
+* Done! Now you can compile your tests.
+
+If you have any problem, go to the official repository to find help.
+
+Ps.: Some distros already have googletest packed. If your distro supports it,
+you can use it instead of compile.
+
+Create new unit test
+=======================
+
+If you want to add new unit tests for Yosys, just follow the steps below:
+
+* Go to directory "yosys/test/unit/"
+* In this directory you can find something similar Yosys's directory structure.
+  To create your unit test file you have to follow this pattern:
+  fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the
+  unit test for kernel/celledges.cc, you will need to create a file like this:
+  tests/unit/kernel/celledgesTest.cc;
+* Implement your unit test
+* If you want to compile your tests, just go to yosys root directory and type:
+```
+make unit-test
+```
+
+Run unit test
+=============
+
+To run all unit tests, you need to compile it first and then run it. Follow the
+steps below (from the yosys root directory):
+```
+make unit-test
+make run-all-unitest
+```
+
+If you want to remove all unit test files, type:
+```
+make clean-unit-test
+```

From e6ab00d419ae12d7d985e2bd671bdfc74167b863 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 5 Dec 2016 20:10:03 -0800
Subject: [PATCH 03/35] Updated help text for synth_greenpak4

---
 techlibs/greenpak4/synth_greenpak4.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 10e2a1498..dac256822 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -36,6 +36,8 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		log("    synth_greenpak4 [options]\n");
 		log("\n");
 		log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
+		log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
+		log("place-and-route.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");

From 981f01430190aeba2c27dd516cefb5730063fcc7 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 5 Dec 2016 21:22:41 -0800
Subject: [PATCH 04/35] Initial implementation of techlib support for GreenPAK
 latches. Instantiation only, no behavioral inference yet.

---
 techlibs/greenpak4/cells_map.v | 52 ++++++++++++++++++++++++++
 techlibs/greenpak4/cells_sim.v | 68 ++++++++++++++++++++++++++++++++++
 2 files changed, 120 insertions(+)

diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index 111a77a14..f8fb2569a 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -50,6 +50,58 @@ module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 	);
 endmodule
 
+module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSR #(
+		.INIT(INIT),
+		.SRMODE(1'b1),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nSET),
+		.Q(Q)
+	);
+endmodule
+
+module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSR #(
+		.INIT(INIT),
+		.SRMODE(1'b0),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nRST),
+		.Q(Q)
+	);
+endmodule
+
+module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSRI #(
+		.INIT(INIT),
+		.SRMODE(1'b1),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nSET),
+		.nQ(nQ)
+	);
+endmodule
+
+module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSRI #(
+		.INIT(INIT),
+		.SRMODE(1'b0),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nRST),
+		.nQ(nQ)
+	);
+endmodule
+
 module GP_OBUFT(input IN, input OE, output OUT);
 	GP_IOBUF _TECHMAP_REPLACE_ (
 		.IN(IN),
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 80746be0f..1b3a66038 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -240,6 +240,74 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 	end
 endmodule
 
+module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nRST)
+			Q <= 1'b0;
+		else if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nRST)
+			Q <= 1'b1;
+		else if(!nCLK)
+			Q <= ~D;
+	end
+endmodule
+
+module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nSET)
+			Q <= 1'b1;
+		else if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nSET)
+			Q <= 1'b0;
+		else if(!nCLK)
+			Q <= ~D;
+	end
+endmodule
+
+module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	parameter[0:0] SRMODE = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nSR)
+			Q <= SRMODE;
+		else if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	parameter[0:0] SRMODE = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nSR)
+			Q <= ~SRMODE;
+		else if(!nCLK)
+			Q <= ~D;
+	end
+endmodule
+
 module GP_EDGEDET(input IN, output reg OUT);
 
 	parameter EDGE_DIRECTION = "RISING";

From 8767cdcac95d30a454ba2bdd7c0d81083d3215ec Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 5 Dec 2016 23:49:06 -0800
Subject: [PATCH 05/35] Added GP_DLATCH and GP_DLATCHI

---
 techlibs/greenpak4/cells_sim.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1b3a66038..a59d17154 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -240,6 +240,24 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 	end
 endmodule
 
+module GP_DLATCH(input D, input nCLK, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHI(input D, input nCLK, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nCLK)
+			Q <= ~D;
+	end
+endmodule
+
 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 	parameter [0:0] INIT = 1'bx;
 	initial Q = INIT;

From 797c03997e2e87416d7486197b079b6c273e2fa6 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sat, 10 Dec 2016 13:57:37 +0800
Subject: [PATCH 06/35] greenpak4: Inverted D latch cells now have nQ instead
 of Q as output port name for consistency

---
 techlibs/greenpak4/cells_sim.v | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index a59d17154..ca3e6cdbf 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -249,12 +249,12 @@ module GP_DLATCH(input D, input nCLK, output reg Q);
 	end
 endmodule
 
-module GP_DLATCHI(input D, input nCLK, output reg Q);
+module GP_DLATCHI(input D, input nCLK, output reg nQ);
 	parameter [0:0] INIT = 1'bx;
-	initial Q = INIT;
+	initial nQ = INIT;
 	always @(*) begin
 		if(!nCLK)
-			Q <= ~D;
+			nQ <= ~D;
 	end
 endmodule
 
@@ -269,14 +269,14 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 	end
 endmodule
 
-module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q);
+module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 	parameter [0:0] INIT = 1'bx;
-	initial Q = INIT;
+	initial nQ = INIT;
 	always @(*) begin
 		if(!nRST)
-			Q <= 1'b1;
+			nQ <= 1'b1;
 		else if(!nCLK)
-			Q <= ~D;
+			nQ <= ~D;
 	end
 endmodule
 
@@ -291,14 +291,14 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 	end
 endmodule
 
-module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q);
+module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 	parameter [0:0] INIT = 1'bx;
-	initial Q = INIT;
+	initial nQ = INIT;
 	always @(*) begin
 		if(!nSET)
-			Q <= 1'b0;
+			nQ <= 1'b0;
 		else if(!nCLK)
-			Q <= ~D;
+			nQ <= ~D;
 	end
 endmodule
 
@@ -314,15 +314,15 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 	end
 endmodule
 
-module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q);
+module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 	parameter [0:0] INIT = 1'bx;
 	parameter[0:0] SRMODE = 1'bx;
-	initial Q = INIT;
+	initial nQ = INIT;
 	always @(*) begin
 		if(!nSR)
-			Q <= ~SRMODE;
+			nQ <= ~SRMODE;
 		else if(!nCLK)
-			Q <= ~D;
+			nQ <= ~D;
 	end
 endmodule
 

From c53a33143efc0ba2ee38fdb9f2ab8a4f16bde4b8 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sat, 10 Dec 2016 18:46:36 +0800
Subject: [PATCH 07/35] greenpak4: Can now techmap inferred D latches (without
 set/reset or output inverter)

---
 techlibs/greenpak4/Makefile.inc       |  1 +
 techlibs/greenpak4/cells_latch.v      | 15 +++++++++++++++
 techlibs/greenpak4/synth_greenpak4.cc |  1 +
 3 files changed, 17 insertions(+)
 create mode 100644 techlibs/greenpak4/cells_latch.v

diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 1c9871e2f..7482af6c6 100644
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/greenpak4/synth_greenpak4.o
 OBJS += techlibs/greenpak4/greenpak4_counters.o
 OBJS += techlibs/greenpak4/greenpak4_dffinv.o
 
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
diff --git a/techlibs/greenpak4/cells_latch.v b/techlibs/greenpak4/cells_latch.v
new file mode 100644
index 000000000..2ccdd2031
--- /dev/null
+++ b/techlibs/greenpak4/cells_latch.v
@@ -0,0 +1,15 @@
+module $_DLATCH_P_(input E, input D, output Q);
+	GP_DLATCH _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(!E),
+		.Q(Q)
+		);
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+	GP_DLATCH _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(E),
+		.Q(Q)
+		);
+endmodule
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index dac256822..be12ab495 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -161,6 +161,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 			run("memory_map");
 			run("opt -undriven -fine");
 			run("techmap");
+			run("techmap -map +/greenpak4/cells_latch.v");
 			run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 			run("opt -fast");
 			if (retime || help_mode)

From 8f3d1f8fcfb5f853b1dfddc1073b4e79a81d6bd8 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sat, 10 Dec 2016 19:58:32 +0800
Subject: [PATCH 08/35] greenpak4: Added support for inferred input/output
 inverters on latches

---
 techlibs/greenpak4/greenpak4_dffinv.cc | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index ff63958e6..7d9d7d5b0 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
 void invert_gp_dff(Cell *cell, bool invert_input)
 {
 	string cell_type = cell->type.str();
+	bool cell_type_latch = cell_type.find("LATCH") != string::npos;
 	bool cell_type_i = cell_type.find('I') != string::npos;
 	bool cell_type_r = cell_type.find('R') != string::npos;
 	bool cell_type_s = cell_type.find('S') != string::npos;
@@ -79,25 +80,28 @@ void invert_gp_dff(Cell *cell, bool invert_input)
 		cell_type_i = true;
 	}
 
-	cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+	if(cell_type_latch)
+		cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+	else
+		cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
 
 	log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
 			log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
 }
 
 struct Greenpak4DffInvPass : public Pass {
-	Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFFs") { }
+	Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
 	virtual void help()
 	{
 		log("\n");
 		log("    greenpak4_dffinv [options] [selection]\n");
 		log("\n");
-		log("Merge GP_INV cells with GP_DFF* cells.\n");
+		log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header(design, "Executing GREENPAK4_DFFINV pass (merge synchronous set/reset into FF cells).\n");
+		log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -120,6 +124,15 @@ struct Greenpak4DffInvPass : public Pass {
 		gp_dff_types.insert("\\GP_DFFSR");
 		gp_dff_types.insert("\\GP_DFFSRI");
 
+		gp_dff_types.insert("\\GP_DLATCH");
+		gp_dff_types.insert("\\GP_DLATCHI");
+		gp_dff_types.insert("\\GP_DLATCHR");
+		gp_dff_types.insert("\\GP_DLATCHRI");
+		gp_dff_types.insert("\\GP_DLATCHS");
+		gp_dff_types.insert("\\GP_DLATCHSI");
+		gp_dff_types.insert("\\GP_DLATCHSR");
+		gp_dff_types.insert("\\GP_DLATCHSRI");
+
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);

From b932e2355de3d2d3b7a61fe86d11265ba02aba2a Mon Sep 17 00:00:00 2001
From: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Date: Sat, 10 Dec 2016 18:21:56 -0200
Subject: [PATCH 09/35] Improved unit test structure

Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>

* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
---
 CodingReadme        |  4 ++--
 Makefile            |  3 ---
 tests/unit/Makefile | 29 ++++++++++++++++++-----------
 3 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/CodingReadme b/CodingReadme
index d2e975dab..041f3b1fa 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -436,8 +436,8 @@ test. However, it is strongly recommended that you take a look to the official
 repository (https://github.com/google/googletest) and refers to that if you
 have any problem to install it. Follow the steps below:
 
-* Install: cmake
-* Clone google test project from: //github.com/rodrigosiqueira/logbook.git and
+* Install: cmake and pthread
+* Clone google test project from: https://github.com/google/googletest and
   enter in the project directory
 * Inside project directory, type:
 
diff --git a/Makefile b/Makefile
index 340fe1229..cf40309ce 100644
--- a/Makefile
+++ b/Makefile
@@ -455,9 +455,6 @@ unit-test: libyosys.so
 	@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
 		CXXFLAGS="$(CXXFLAGS)" LDLIBS="$(LDLIBS)" ROOTPATH="$(CURDIR)"
 
-run-all-unitest:
-	@$(MAKE) -C $(UNITESTPATH) run-tests
-
 clean-unit-test:
 	@$(MAKE) -C $(UNITESTPATH) clean
 
diff --git a/tests/unit/Makefile b/tests/unit/Makefile
index 16f65ec20..447a5f619 100644
--- a/tests/unit/Makefile
+++ b/tests/unit/Makefile
@@ -2,26 +2,33 @@ GTESTFLAG := -lgtest -lgtest_main
 RPATH := -Wl,-rpath
 EXTRAFLAGS := -lyosys
 
-ALLTESTFILE := $(wildcard ./**/*Test.cc)
 OBJTEST := objtest
 BINTEST := bintest
 
-all: prepare $(ALLTESTFILE:%Test.cc=%Test.o)
+ALLTESTFILE := $(shell find -name '*Test.cc' -printf '%P ')
+TESTDIRS := $(sort $(dir $(ALLTESTFILE)))
+TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o)))
 
-%Test.o: %Test.cc
-	$(CXX) -o $(OBJTEST)/$(notdir $@) -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $<
-	$(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) -o \
-		$(BINTEST)/$(basename $(notdir $@)) $(OBJTEST)/$(notdir $@) $(LDLIBS) \
+# Prevent make from removing our .o files
+.SECONDARY:
+
+all: prepare $(TESTS) run-tests
+
+$(BINTEST)/%: $(OBJTEST)/%.o
+	$(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) -o $@ $^ $(LDLIBS) \
 		$(GTESTFLAG) $(EXTRAFLAGS)
-	
+
+$(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc
+	$(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $^
+
 .PHONY: prepare run-tests clean
 
-run-tests:
-	$(CURDIR)/$(BINTEST)/*
+run-tests: $(TESTS)
+	$(subst Test ,Test; ,$^)
 
 prepare:
-	mkdir -p $(OBJTEST)
-	mkdir -p $(BINTEST)
+	mkdir -p $(addprefix $(BINTEST)/,$(TESTDIRS))
+	mkdir -p $(addprefix $(OBJTEST)/,$(TESTDIRS))
 
 clean:
 	rm -rf $(OBJTEST)

From c3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 11 Dec 2016 10:04:00 +0800
Subject: [PATCH 10/35] Added GP_PWRDET block, BANDWIDTH_KHZ parameter to
 GP_ABUF

---
 techlibs/greenpak4/cells_sim.v | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index ca3e6cdbf..1b899e8e8 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -18,7 +18,11 @@ endmodule
 module GP_ABUF(input wire IN, output wire OUT);
 	
 	assign OUT = IN;
-	
+
+	//must be 1, 5, 20, 50
+	//values >1 only available with Vdd > 2.7V
+	parameter BANDWIDTH_KHZ = 1;
+
 	//cannot simulate mixed signal IP
 	
 endmodule
@@ -412,6 +416,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 	
 endmodule
 
+module GP_PWRDET(output reg VDD_LOW);
+	initial VDD_LOW = 0;
+endmodule
+
 module GP_POR(output reg RST_DONE);
 	parameter POR_TIME = 500;
 	

From 5c96982522779fef5b63bcc16297e6633dafff03 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 11 Dec 2016 10:58:49 +0100
Subject: [PATCH 11/35] Build hotfix in tests/unit/Makefile

---
 tests/unit/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/unit/Makefile b/tests/unit/Makefile
index 447a5f619..9f1e5c99e 100644
--- a/tests/unit/Makefile
+++ b/tests/unit/Makefile
@@ -1,6 +1,6 @@
 GTESTFLAG := -lgtest -lgtest_main
 RPATH := -Wl,-rpath
-EXTRAFLAGS := -lyosys
+EXTRAFLAGS := -lyosys -pthreads
 
 OBJTEST := objtest
 BINTEST := bintest

From 71c47f13ed15d4635a408832d69f0cfb6b35443e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 11 Dec 2016 11:02:56 +0100
Subject: [PATCH 12/35] Some minor CodingReadme changes in unit test section

---
 CodingReadme | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/CodingReadme b/CodingReadme
index 041f3b1fa..9e85add28 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -429,7 +429,7 @@ well with C/C++ code.  Hence, it was chosen (google test)
 relatively easy learn.
 
 Install and configure google test (manually)
-============================================
+--------------------------------------------
 
 In this section, you will see a brief description of how to install google
 test. However, it is strongly recommended that you take a look to the official
@@ -456,7 +456,7 @@ Ps.: Some distros already have googletest packed. If your distro supports it,
 you can use it instead of compile.
 
 Create new unit test
-=======================
+--------------------
 
 If you want to add new unit tests for Yosys, just follow the steps below:
 
@@ -467,19 +467,13 @@ If you want to add new unit tests for Yosys, just follow the steps below:
   unit test for kernel/celledges.cc, you will need to create a file like this:
   tests/unit/kernel/celledgesTest.cc;
 * Implement your unit test
-* If you want to compile your tests, just go to yosys root directory and type:
-```
-make unit-test
-```
 
 Run unit test
-=============
+-------------
 
-To run all unit tests, you need to compile it first and then run it. Follow the
-steps below (from the yosys root directory):
+To compile and run all unit tests, just go to yosys root directory and type:
 ```
 make unit-test
-make run-all-unitest
 ```
 
 If you want to remove all unit test files, type:

From a61c88f12215eb8bfa1db62aec7c2c95bb3cc702 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 11 Dec 2016 13:48:18 +0100
Subject: [PATCH 13/35] Added $anyconst support to AIGER back-end

---
 backends/aiger/aiger.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index aefe5cf43..ab1fba6f1 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -163,6 +163,13 @@ struct AigerWriter
 				continue;
 			}
 
+			if (cell->type == "$anyconst")
+			{
+				for (auto bit : sigmap(cell->getPort("\\Y")))
+					ff_map[bit] = bit;
+				continue;
+			}
+
 			log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}
 

From 00761de1b7c59868c875312cc4ef330e97a2a4de Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 13 Dec 2016 13:48:09 +0100
Subject: [PATCH 14/35] Bugfix in comment handling

---
 kernel/register.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/register.cc b/kernel/register.cc
index 7a1d0b44b..983577682 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -173,7 +173,7 @@ void Pass::call(RTLIL::Design *design, std::string command)
 	}
 
 	while (!tok.empty()) {
-		if (tok == "#") {
+		if (tok[0] == '#') {
 			int stop;
 			for (stop = 0; stop < GetSize(cmd_buf); stop++)
 				if (cmd_buf[stop] == '\r' || cmd_buf[stop] == '\n')

From c77e6e6114f4489ce4801c9593e0eea42e485ae5 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Wed, 14 Dec 2016 14:14:26 +0800
Subject: [PATCH 15/35] greenpak4: Added GP_DCMPREF / GP_DCMPMUX

---
 techlibs/greenpak4/cells_sim.v | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1b899e8e8..b5932fef5 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -132,6 +132,29 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
+module GP_DCMPREF(output OUT)
+	parameter[7:0] REF_VAL = 8'h00;
+	wire[7:0] OUT = REF_VAL;
+endmodule
+
+module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT)
+	wire[1:0] SEL;
+	wire[7:0] IN0;
+	wire[7:0] IN1;
+	wire[7:0] IN2;
+	wire[7:0] IN3;
+	reg[7:0] OUT;
+
+	always @(*) begin
+		case(SEL)
+			2'b00: OUT <= IN0;
+			2'b10: OUT <= IN1;
+			2'b01: OUT <= IN2;
+			2'b11: OUT <= IN3;
+		end
+	end
+endmodule
+
 module GP_DELAY(input IN, output reg OUT);
 	
 	parameter DELAY_STEPS = 1;

From 262f8f913cd7b72fa86b0465590c8f6ad9e2d036 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Wed, 14 Dec 2016 14:14:45 +0800
Subject: [PATCH 16/35] greenpak4: Cleaned up trailing spaces in cells_sim

---
 techlibs/greenpak4/cells_sim.v | 120 ++++++++++++++++-----------------
 1 file changed, 60 insertions(+), 60 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index b5932fef5..83727e9b2 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -16,7 +16,7 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
 endmodule
 
 module GP_ABUF(input wire IN, output wire OUT);
-	
+
 	assign OUT = IN;
 
 	//must be 1, 5, 20, 50
@@ -24,7 +24,7 @@ module GP_ABUF(input wire IN, output wire OUT);
 	parameter BANDWIDTH_KHZ = 1;
 
 	//cannot simulate mixed signal IP
-	
+
 endmodule
 
 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
@@ -33,9 +33,9 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT
 	parameter VIN_ATTEN = 1;
 	parameter VIN_ISRC_EN = 0;
 	parameter HYSTERESIS = 0;
-	
+
 	initial OUT = 0;
-	
+
 	//cannot simulate mixed signal IP
 
 endmodule
@@ -44,37 +44,37 @@ module GP_BANDGAP(output reg OK);
 	parameter AUTO_PWRDN = 1;
 	parameter CHOPPER_EN = 1;
 	parameter OUT_DELAY = 100;
-	
+
 	//cannot simulate mixed signal IP
-	
+
 endmodule
 
 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 
-	parameter RESET_MODE 	= "RISING";	
-	
+	parameter RESET_MODE 	= "RISING";
+
 	parameter COUNT_TO		= 8'h1;
 	parameter CLKIN_DIVIDE	= 1;
-	
+
 	//more complex hard IP blocks are not supported for simulation yet
-	
+
 	reg[7:0] count = COUNT_TO;
-	
+
 	//Combinatorially output whenever we wrap low
 	always @(*) begin
 		OUT <= (count == 8'h0);
 	end
-	
+
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
 	//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
 	//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
 	always @(posedge CLK) begin
-		
+
 		count		<= count - 1'd1;
-		
+
 		if(count == 0)
 			count	<= COUNT_TO;
-			
+
 		/*
 		if((RESET_MODE == "RISING") && RST)
 			count	<= 0;
@@ -82,18 +82,18 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 			count	<= 0;
 		if((RESET_MODE == "BOTH") && RST)
 			count	<= 0;
-		*/			
+		*/
 	end
 
 endmodule
 
 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
-	parameter RESET_MODE 	= "RISING";	
-	
+	parameter RESET_MODE 	= "RISING";
+
 	parameter COUNT_TO		= 14'h1;
 	parameter CLKIN_DIVIDE	= 1;
-	
+
 	//more complex hard IP blocks are not supported for simulation yet
 
 endmodule
@@ -156,14 +156,14 @@ module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output
 endmodule
 
 module GP_DELAY(input IN, output reg OUT);
-	
+
 	parameter DELAY_STEPS = 1;
 	parameter GLITCH_FILTER = 0;
-		
+
 	initial OUT = 0;
-	
+
 	generate
-		
+
 		//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 		//Change simulation-mode delay depending on global Vdd range (how to specify this?)
 		always @(*) begin
@@ -178,9 +178,9 @@ module GP_DELAY(input IN, output reg OUT);
 				end
 			endcase
 		end
-		
+
 	endgenerate
-	
+
 endmodule
 
 module GP_DFF(input D, CLK, output reg Q);
@@ -358,9 +358,9 @@ module GP_EDGEDET(input IN, output reg OUT);
 	parameter EDGE_DIRECTION = "RISING";
 	parameter DELAY_STEPS = 1;
 	parameter GLITCH_FILTER = 0;
-	
+
 	//not implemented for simulation
-	
+
 endmodule
 
 module GP_IBUF(input IN, output OUT);
@@ -377,16 +377,16 @@ module GP_INV(input IN, output OUT);
 endmodule
 
 module GP_LFOSC(input PWRDN, output reg CLKOUT);
-	
+
 	parameter PWRDN_EN = 0;
 	parameter AUTO_PWRDN = 0;
 	parameter OUT_DIV = 1;
-	
+
 	initial CLKOUT = 0;
-	
+
 	//auto powerdown not implemented for simulation
 	//output dividers not implemented for simulation
-	
+
 	always begin
 		if(PWRDN)
 			CLKOUT = 0;
@@ -396,7 +396,7 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
 			CLKOUT = ~CLKOUT;
 		end
 	end
-	
+
 endmodule
 
 module GP_OBUF(input IN, output OUT);
@@ -433,10 +433,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 			OUT <= PATTERN_DATA[count];
 
 			if( (count + 1) == PATTERN_LEN)
-				count <= 0;			
+				count <= 0;
 		end
 	end
-	
+
 endmodule
 
 module GP_PWRDET(output reg VDD_LOW);
@@ -445,10 +445,10 @@ endmodule
 
 module GP_POR(output reg RST_DONE);
 	parameter POR_TIME = 500;
-	
+
 	initial begin
 		RST_DONE = 0;
-		
+
 		if(POR_TIME == 4)
 			#4000;
 		else if(POR_TIME == 500)
@@ -457,64 +457,64 @@ module GP_POR(output reg RST_DONE);
 			$display("ERROR: bad POR_TIME for GP_POR cell");
 			$finish;
 		end
-		
+
 		RST_DONE = 1;
-		
+
 	end
-	
+
 endmodule
 
 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
-	
+
 	parameter PWRDN_EN = 0;
 	parameter AUTO_PWRDN = 0;
 	parameter HARDIP_DIV = 1;
 	parameter FABRIC_DIV = 1;
 	parameter OSC_FREQ = "25k";
-	
+
 	initial CLKOUT_HARDIP = 0;
 	initial CLKOUT_FABRIC = 0;
-	
+
 	//output dividers not implemented for simulation
 	//auto powerdown not implemented for simulation
-	
+
 	always begin
 		if(PWRDN) begin
 			CLKOUT_HARDIP = 0;
 			CLKOUT_FABRIC = 0;
 		end
 		else begin
-		
+
 			if(OSC_FREQ == "25k") begin
 				//half period of 25 kHz
 				#20000;
 			end
-			
+
 			else begin
 				//half period of 2 MHz
 				#250;
 			end
-			
+
 			CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 		end
 	end
-	
+
 endmodule
 
 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
-	
+
 	parameter PWRDN_EN = 0;
 	parameter AUTO_PWRDN = 0;
 	parameter HARDIP_DIV = 1;
 	parameter FABRIC_DIV = 1;
-	
+
 	initial CLKOUT_HARDIP = 0;
 	initial CLKOUT_FABRIC = 0;
-	
+
 	//output dividers not implemented for simulation
 	//auto powerdown not implemented for simulation
-	
+
 	always begin
 		if(PWRDN) begin
 			CLKOUT_HARDIP = 0;
@@ -527,7 +527,7 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRI
 			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 		end
 	end
-	
+
 endmodule
 
 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
@@ -535,19 +535,19 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 	parameter OUTA_TAP = 1;
 	parameter OUTA_INVERT = 0;
 	parameter OUTB_TAP = 1;
-	
+
 	reg[15:0] shreg = 0;
-	
+
 	always @(posedge CLK, negedge nRST) begin
-		
+
 		if(!nRST)
 			shreg = 0;
-		
+
 		else
 			shreg <= {shreg[14:0], IN};
-		
+
 	end
-	
+
 	assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 	assign OUTB = shreg[OUTB_TAP - 1];
 
@@ -558,9 +558,9 @@ endmodule
 module GP_SYSRESET(input RST);
 	parameter RESET_MODE = "EDGE";
 	parameter EDGE_SPEED = 4;
-	
+
 	//cannot simulate whole system reset
-	
+
 endmodule
 
 module GP_VDD(output OUT);

From 58da621ac3892bda42e31faa6ac4f02bc9cf3f87 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 15 Dec 2016 07:15:38 +0800
Subject: [PATCH 17/35] greenpak4: Fixed typo

---
 techlibs/greenpak4/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 83727e9b2..d5a06a453 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -132,7 +132,7 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
-module GP_DCMPREF(output OUT)
+module GP_DCMPREF(output OUT);
 	parameter[7:0] REF_VAL = 8'h00;
 	wire[7:0] OUT = REF_VAL;
 endmodule

From ea787e6be3d8559dbf9994d73283d9a234273fe9 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 15 Dec 2016 07:16:26 +0800
Subject: [PATCH 18/35] greenpak4: Fixed another typo

---
 techlibs/greenpak4/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index d5a06a453..65f4a6f70 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -137,7 +137,7 @@ module GP_DCMPREF(output OUT);
 	wire[7:0] OUT = REF_VAL;
 endmodule
 
-module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT)
+module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT);
 	wire[1:0] SEL;
 	wire[7:0] IN0;
 	wire[7:0] IN1;

From 3491d338634b76639d46770c04f907ac60f19a96 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 15 Dec 2016 07:17:07 +0800
Subject: [PATCH 19/35] greenpak4: And another typo :(

---
 techlibs/greenpak4/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 65f4a6f70..25a49ac06 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -151,7 +151,7 @@ module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output
 			2'b10: OUT <= IN1;
 			2'b01: OUT <= IN2;
 			2'b11: OUT <= IN3;
-		end
+		endcase
 	end
 endmodule
 

From 3690aa556c5f1e51634fe2fc51cbffd174e76480 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 15 Dec 2016 07:19:08 +0800
Subject: [PATCH 20/35] greenpak4: More fixups of GP_DCMPx cells

---
 techlibs/greenpak4/cells_sim.v | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 25a49ac06..cd5086951 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -132,18 +132,12 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
-module GP_DCMPREF(output OUT);
+module GP_DCMPREF(output reg[7:0]OUT);
 	parameter[7:0] REF_VAL = 8'h00;
-	wire[7:0] OUT = REF_VAL;
+	initial OUT = REF_VAL;
 endmodule
 
-module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT);
-	wire[1:0] SEL;
-	wire[7:0] IN0;
-	wire[7:0] IN1;
-	wire[7:0] IN2;
-	wire[7:0] IN3;
-	reg[7:0] OUT;
+module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUT);
 
 	always @(*) begin
 		case(SEL)

From bea6e2f11fefc9e93fef6e1cf41bcc3361cc5412 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 15 Dec 2016 15:19:35 +0800
Subject: [PATCH 21/35] greenpak4: Initial version of GP_DCMP skeleton (not yet
 usable). Changed interface to GP_DCMPMUX

---
 techlibs/greenpak4/cells_sim.v | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index cd5086951..14c442cb4 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -132,19 +132,38 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
+module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN);
+endmodule
+
 module GP_DCMPREF(output reg[7:0]OUT);
 	parameter[7:0] REF_VAL = 8'h00;
 	initial OUT = REF_VAL;
 endmodule
 
-module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUT);
+module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
 
 	always @(*) begin
 		case(SEL)
-			2'b00: OUT <= IN0;
-			2'b10: OUT <= IN1;
-			2'b01: OUT <= IN2;
-			2'b11: OUT <= IN3;
+			2'b00: begin
+				OUTA <= IN0;
+				OUTB <= IN3;
+			end
+
+			2'b01: begin
+				OUTA <= IN1;
+				OUTB <= IN2;
+			end
+
+			2'b02: begin
+				OUTA <= IN2;
+				OUTB <= IN1;
+			end
+
+			2'b03: begin
+				OUTA <= IN3;
+				OUTB <= IN0;
+			end
+
 		endcase
 	end
 endmodule

From 3886669ab6dc25926fcac1802d0a2176599a7fbf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 15 Dec 2016 17:49:11 +0100
Subject: [PATCH 22/35] Added "verilog_defines" command

---
 frontends/verilog/verilog_frontend.cc | 60 +++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 2a1dce389..fe84c8e80 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -436,6 +436,66 @@ struct VerilogDefaults : public Pass {
 	}
 } VerilogDefaults;
 
+struct VerilogDefines : public Pass {
+	VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
+	virtual void help()
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    verilog_defines [options]\n");
+		log("\n");
+		log("Define and undefine verilog preprocessor macros.\n");
+		log("\n");
+		log("    -Dname[=definition]\n");
+		log("        define the preprocessor symbol 'name' and set its optional value\n");
+		log("        'definition'\n");
+		log("\n");
+		log("    -Uname[=definition]\n");
+		log("        undefine the preprocessor symbol 'name'\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-D" && argidx+1 < args.size()) {
+				std::string name = args[++argidx], value;
+				size_t equal = name.find('=');
+				if (equal != std::string::npos) {
+					value = name.substr(equal+1);
+					name = name.substr(0, equal);
+				}
+				design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
+				continue;
+			}
+			if (arg.compare(0, 2, "-D") == 0) {
+				size_t equal = arg.find('=', 2);
+				std::string name = arg.substr(2, equal-2);
+				std::string value;
+				if (equal != std::string::npos)
+					value = arg.substr(equal+1);
+				design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
+				continue;
+			}
+			if (arg == "-U" && argidx+1 < args.size()) {
+				std::string name = args[++argidx];
+				design->verilog_defines.erase(name);
+				continue;
+			}
+			if (arg.compare(0, 2, "-U") == 0) {
+				std::string name = arg.substr(2);
+				design->verilog_defines.erase(name);
+				continue;
+			}
+			break;
+		}
+
+		if (args.size() != argidx)
+			cmd_error(args, argidx, "Extra argument.");
+	}
+} VerilogDefines;
+
 YOSYS_NAMESPACE_END
 
 // the yyerror function used by bison to report parser errors

From 7cdba8432cae3ebd076b13d3b2b17d40683ef97a Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Fri, 16 Dec 2016 15:14:20 +0800
Subject: [PATCH 23/35] greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.

---
 techlibs/greenpak4/cells_sim.v | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 14c442cb4..0f1eaf8fb 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -49,6 +49,10 @@ module GP_BANDGAP(output reg OK);
 
 endmodule
 
+module GP_CLKBUF(input wire IN, output wire OUT);
+	assign OUT = IN;
+endmodule
+
 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 
 	parameter RESET_MODE 	= "RISING";
@@ -132,7 +136,8 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
-module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN);
+module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN);
+	//TODO finish implementing
 endmodule
 
 module GP_DCMPREF(output reg[7:0]OUT);
@@ -144,22 +149,22 @@ module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2
 
 	always @(*) begin
 		case(SEL)
-			2'b00: begin
+			2'd00: begin
 				OUTA <= IN0;
 				OUTB <= IN3;
 			end
 
-			2'b01: begin
+			2'd01: begin
 				OUTA <= IN1;
 				OUTB <= IN2;
 			end
 
-			2'b02: begin
+			2'd02: begin
 				OUTA <= IN2;
 				OUTB <= IN1;
 			end
 
-			2'b03: begin
+			2'd03: begin
 				OUTA <= IN3;
 				OUTB <= IN0;
 			end

From de1d81511af7a5ca362c334635190609c45e998b Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sat, 17 Dec 2016 12:01:22 +0800
Subject: [PATCH 24/35] greenpak4: Updated GP_DCMP cell model

---
 techlibs/greenpak4/cells_sim.v | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 0f1eaf8fb..27c5ff054 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -136,8 +136,26 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
-module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN);
-	//TODO finish implementing
+module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
+	parameter PWRDN_SYNC = 1'b0;
+	parameter CLK_EDGE = "RISING";
+	parameter GREATER_OR_EQUAL = 1'b0;
+
+	//TODO implement power-down mode
+
+	initial GREATER = 0;
+	initial EQUAL = 0;
+
+	wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
+	always @(posedge clk_minv) begin
+		if(GREATER_OR_EQUAL)
+			GREATER <= (INP >= INN);
+		else
+			GREATER <= (INP > INN);
+
+		EQUAL <= (INP == INN);
+	end
+
 endmodule
 
 module GP_DCMPREF(output reg[7:0]OUT);

From eb80ec84aaa8789d554a1246e8d07c33d2882974 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 20 Dec 2016 09:58:02 +0800
Subject: [PATCH 25/35] greenpak4: Initial implementation of GP_SPI cell

---
 techlibs/greenpak4/cells_sim.v | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 27c5ff054..6b8280eb2 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -589,6 +589,33 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 
 endmodule
 
+module GP_SPI(
+	input SCK,
+	input MOSI,
+	input CSN,
+	output reg MISO,
+	input[7:0] DIN_HIGH,
+	input[7:0] DIN_LOW,
+	output reg[7:0] DOUT_HIGH,
+	output reg[7:0] DOUT_LOW);
+
+	initial MISO = 0;
+	initial DOUT_HIGH = 0;
+	initial DOUT_LOW = 0;
+
+	parameter ADC_BUFFER = 0;		//set true to use SPI data as ADC buffer... TODO
+	parameter DATA_WIDTH = 8;		//byte or word width
+	parameter SPI_CPHA = 0;			//SPI clock phase
+	parameter SPI_CPOL = 0;			//SPI clock polarity
+	parameter DIRECTION = "INPUT";	//SPI data direction (either input to chip or output to host)
+	//parallel output to fabric not yet implemented
+
+	//TODO: write sim model
+	//TODO: SPI SDIO control... can we use ADC output while SPI is input??
+	//TODO: clock sync
+
+endmodule
+
 //keep constraint needed to prevent optimization since we have no outputs
 (* keep *)
 module GP_SYSRESET(input RST);

From d4a05b499e58db500c376e3c44e4a1e4c46542c3 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 20 Dec 2016 10:30:38 +0800
Subject: [PATCH 26/35] greenpak4: Changed port names on GP_SPI for clarity

---
 techlibs/greenpak4/cells_sim.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 6b8280eb2..b3060b14a 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -594,10 +594,10 @@ module GP_SPI(
 	input MOSI,
 	input CSN,
 	output reg MISO,
-	input[7:0] DIN_HIGH,
-	input[7:0] DIN_LOW,
-	output reg[7:0] DOUT_HIGH,
-	output reg[7:0] DOUT_LOW);
+	input[7:0] TXD_HIGH,
+	input[7:0] TXD_LOW,
+	output reg[7:0] RXD_HIGH,
+	output reg[7:0] RXD_LOW);
 
 	initial MISO = 0;
 	initial DOUT_HIGH = 0;

From 073e8df9f1ca88ae30f5c61f7a620b02210e1747 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 20 Dec 2016 12:34:56 +0800
Subject: [PATCH 27/35] greenpak4: replaced MOSI/MISO with single one-way SDAT
 pin

---
 techlibs/greenpak4/cells_sim.v | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index b3060b14a..3263c4ebc 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -591,7 +591,7 @@ endmodule
 
 module GP_SPI(
 	input SCK,
-	input MOSI,
+	inout SDAT,
 	input CSN,
 	output reg MISO,
 	input[7:0] TXD_HIGH,
@@ -599,7 +599,6 @@ module GP_SPI(
 	output reg[7:0] RXD_HIGH,
 	output reg[7:0] RXD_LOW);
 
-	initial MISO = 0;
 	initial DOUT_HIGH = 0;
 	initial DOUT_LOW = 0;
 

From 638f3e3b1205b16e6e5fe2e9c611bfd0853d2550 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 20 Dec 2016 13:07:49 +0800
Subject: [PATCH 28/35] greenpak4: Removed SPI_BUFFER parameter

---
 techlibs/greenpak4/cells_sim.v | 1 -
 1 file changed, 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 3263c4ebc..8b22630fe 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -602,7 +602,6 @@ module GP_SPI(
 	initial DOUT_HIGH = 0;
 	initial DOUT_LOW = 0;
 
-	parameter ADC_BUFFER = 0;		//set true to use SPI data as ADC buffer... TODO
 	parameter DATA_WIDTH = 8;		//byte or word width
 	parameter SPI_CPHA = 0;			//SPI clock phase
 	parameter SPI_CPOL = 0;			//SPI clock polarity

From 6b526e93823a72e1b3b2c20a084073477aba399f Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Wed, 21 Dec 2016 11:33:32 +0800
Subject: [PATCH 29/35] greenpak4: removed unused MISO pin from GP_SPI

---
 techlibs/greenpak4/cells_sim.v | 1 -
 1 file changed, 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 8b22630fe..a75ea3fe6 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -593,7 +593,6 @@ module GP_SPI(
 	input SCK,
 	inout SDAT,
 	input CSN,
-	output reg MISO,
 	input[7:0] TXD_HIGH,
 	input[7:0] TXD_LOW,
 	output reg[7:0] RXD_HIGH,

From ada98844b93e29fcbcfada02f89b2882d73182f1 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Wed, 21 Dec 2016 11:35:29 +0800
Subject: [PATCH 30/35] greenpak4: Added INT pin to GP_SPI

---
 techlibs/greenpak4/cells_sim.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index a75ea3fe6..dd21bdd50 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -596,10 +596,12 @@ module GP_SPI(
 	input[7:0] TXD_HIGH,
 	input[7:0] TXD_LOW,
 	output reg[7:0] RXD_HIGH,
-	output reg[7:0] RXD_LOW);
+	output reg[7:0] RXD_LOW,
+	output reg INT);
 
 	initial DOUT_HIGH = 0;
 	initial DOUT_LOW = 0;
+	initial INT = 0;
 
 	parameter DATA_WIDTH = 8;		//byte or word width
 	parameter SPI_CPHA = 0;			//SPI clock phase

From 3d0e51f8139f08c43bf310a6102918b72cde2a8a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 21 Dec 2016 09:13:20 +0100
Subject: [PATCH 31/35] Updated ABC to hg rev 8bab2eedbba4

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index cf40309ce..6fe5eedc6 100644
--- a/Makefile
+++ b/Makefile
@@ -86,7 +86,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 8b555d9e67cf
+ABCREV = 8bab2eedbba4
 ABCPULL = 1
 ABCURL ?= https://bitbucket.org/alanmi/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"

From f31e6a7174243f463db10afb29f7e2d2b140f56c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 21 Dec 2016 10:16:10 +0100
Subject: [PATCH 32/35] Updated ABC to hg rev a4872e22c646

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 6fe5eedc6..ea2395ee9 100644
--- a/Makefile
+++ b/Makefile
@@ -86,7 +86,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 8bab2eedbba4
+ABCREV = a4872e22c646
 ABCPULL = 1
 ABCURL ?= https://bitbucket.org/alanmi/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"

From f144adec587e2d0e993098abc5b576721ba969dd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 21 Dec 2016 10:16:47 +0100
Subject: [PATCH 33/35] Added AIGER back-end to automatic back-end detection

---
 kernel/yosys.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 08fee9741..3d0aca78e 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -903,6 +903,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
 			command = "verilog";
 		else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
 			command = "ilang";
+		else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig")
+			command = "aiger";
 		else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif")
 			command = "blif";
 		else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif")

From a0dff87a5783daa5e47b8089b5e55443dfe11583 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Dec 2016 23:41:44 +0100
Subject: [PATCH 34/35] Added "yosys -W regex"

---
 kernel/driver.cc | 11 ++++++++++-
 kernel/log.cc    | 33 ++++++++++++++++++++++++++++++++-
 kernel/log.h     |  2 ++
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/kernel/driver.cc b/kernel/driver.cc
index f8d00c38d..3652ff4f1 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -218,6 +218,9 @@ int main(int argc, char **argv)
 		printf("        yosys_dump_<header_id>.il is used as filename if none is specified.\n");
 		printf("        Use 'ALL' as <header_id> to dump at every header.\n");
 		printf("\n");
+		printf("    -W regex\n");
+		printf("        print a warning for all log messages matching the regex \n");
+		printf("\n");
 		printf("    -V\n");
 		printf("        print version information and exit\n");
 		printf("\n");
@@ -238,7 +241,7 @@ int main(int argc, char **argv)
 	}
 
 	int opt;
-	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:D:")) != -1)
+	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:D:")) != -1)
 	{
 		switch (opt)
 		{
@@ -320,6 +323,12 @@ int main(int argc, char **argv)
 			scriptfile = optarg;
 			scriptfile_tcl = true;
 			break;
+		case 'W':
+			log_warn_regexes.push_back(std::regex(optarg,
+					std::regex_constants::nosubs |
+					std::regex_constants::optimize |
+					std::regex_constants::egrep));
+			break;
 		case 'D':
 			{
 				auto args = split_tokens(optarg, ":");
diff --git a/kernel/log.cc b/kernel/log.cc
index abc401f55..b3033024f 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -41,6 +41,7 @@ YOSYS_NAMESPACE_BEGIN
 std::vector<FILE*> log_files;
 std::vector<std::ostream*> log_streams;
 std::map<std::string, std::set<std::string>> log_hdump;
+std::vector<std::regex> log_warn_regexes;
 bool log_hdump_all = false;
 FILE *log_errfile = NULL;
 SHA1 *log_hasher = NULL;
@@ -136,6 +137,32 @@ void logv(const char *format, va_list ap)
 
 	for (auto f : log_streams)
 		*f << str;
+
+	static std::string linebuffer;
+	static bool log_warn_regex_recusion_guard = false;
+
+	if (!log_warn_regex_recusion_guard)
+	{
+		log_warn_regex_recusion_guard = true;
+
+		if (log_warn_regexes.empty())
+		{
+			linebuffer.clear();
+		}
+		else
+		{
+			linebuffer += str;
+
+			if (!linebuffer.empty() && linebuffer.back() == '\n') {
+				for (auto &re : log_warn_regexes)
+					if (std::regex_search(linebuffer, re))
+						log_warning("Found log message matching -W regex:\n%s", str.c_str());
+				linebuffer.clear();
+			}
+		}
+
+		log_warn_regex_recusion_guard = false;
+	}
 }
 
 void logv_header(RTLIL::Design *design, const char *format, va_list ap)
@@ -262,8 +289,12 @@ void log_cmd_error(const char *format, ...)
 
 void log_spacer()
 {
-	while (log_newline_count < 2)
+	while (log_newline_count < 2) {
+		int old_log_newline_count = log_newline_count;
 		log("\n");
+		if (old_log_newline_count >= log_newline_count)
+			break;
+	}
 }
 
 void log_push()
diff --git a/kernel/log.h b/kernel/log.h
index 53480db31..5b1729eb1 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -23,6 +23,7 @@
 #define LOG_H
 
 #include <time.h>
+#include <regex>
 
 #ifndef _WIN32
 #  include <sys/time.h>
@@ -48,6 +49,7 @@ struct log_cmd_error_exception { };
 extern std::vector<FILE*> log_files;
 extern std::vector<std::ostream*> log_streams;
 extern std::map<std::string, std::set<std::string>> log_hdump;
+extern std::vector<std::regex> log_warn_regexes;
 extern bool log_hdump_all;
 extern FILE *log_errfile;
 extern SHA1 *log_hasher;

From 33a22f8768ee05325f87258fe09c21c648553747 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 23 Dec 2016 02:06:46 +0100
Subject: [PATCH 35/35] Simplified log_spacer() code

---
 kernel/log.cc | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/kernel/log.cc b/kernel/log.cc
index b3033024f..cd16bb344 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -289,12 +289,8 @@ void log_cmd_error(const char *format, ...)
 
 void log_spacer()
 {
-	while (log_newline_count < 2) {
-		int old_log_newline_count = log_newline_count;
-		log("\n");
-		if (old_log_newline_count >= log_newline_count)
-			break;
-	}
+	if (log_newline_count < 2) log("\n");
+	if (log_newline_count < 2) log("\n");
 }
 
 void log_push()