mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-23 04:38:55 +00:00
Code Activity

verilog: add support for SystemVerilog string literals.

Browse source 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
This commit is contained in:
Gary Wong 2025-07-03 20:51:12 -06:00
parent 7b0c1fe491
commit 5feb1a1752
4 changed files with 386 additions and 47 deletions
Download patch file Download diff file Expand all files Collapse all files

3
docs/source/yosys_internals/verilog.rst
View file

@ -381,3 +381,6 @@ from SystemVerilog:
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)
- SystemVerilog string literals are supported (triple-quoted strings and
escape sequences such as line continuations and hex escapes).