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$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

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This commit is contained in:
Eddie Hung 2019-07-15 12:03:51 -07:00
parent d032198fac
commit 5fb27c071b
7 changed files with 8 additions and 8 deletions
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4
techlibs/ice40/ice40_opt.cc
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@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
continue;
}
if (cell->type == "$__ICE40_CARRY_LUT4")
if (cell->type == "$__ICE40_FULL_ADDER")
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });