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$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

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Eddie Hung 2019-07-15 12:03:51 -07:00
parent d032198fac
commit 5fb27c071b
7 changed files with 8 additions and 8 deletions
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2
techlibs/ice40/cells_sim.v
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@ -142,7 +142,7 @@ module SB_CARRY (output CO, input I0, I1, CI);
endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
SB_CARRY carry (
.I0(A),
.I1(B),