mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Merge pull request #3733 from AdamHillier/aiger-inputs

Browse source 
Add outputs before inputs to the sigmap in the AIGER backend.
This commit is contained in:
Jannis Harder 2023-05-22 16:09:15 +02:00 • committed by GitHub
commit 5fb1223861
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

10
backends/aiger/aiger.cc
View file

@ -119,16 +119,16 @@ struct AigerWriter
if (wire->name.isPublic())
sigmap.add(wire);
// promote input wires
for (auto wire : module->wires())
if (wire->port_input)
sigmap.add(wire);
// promote output wires
for (auto wire : module->wires())
if (wire->port_output)
sigmap.add(wire);
// promote input wires
for (auto wire : module->wires())
if (wire->port_input)
sigmap.add(wire);
for (auto wire : module->wires())
{
if (wire->attributes.count(ID::init)) {