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Preserve 'signed'-ness of a verilog wire through RTLIL

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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
This commit is contained in:
Vamsi K Vytla 2020-04-27 09:44:24 -07:00
parent 3eb24809a1
commit 5f9cd2e2f6
6 changed files with 13 additions and 1 deletions
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2
kernel/rtlil.cc
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@ -1862,6 +1862,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
wire->port_input = other->port_input;
wire->port_output = other->port_output;
wire->upto = other->upto;
wire->is_signed = other->is_signed;
wire->attributes = other->attributes;
return wire;
}
@ -2445,6 +2446,7 @@ RTLIL::Wire::Wire()
port_input = false;
port_output = false;
upto = false;
is_signed = false;
#ifdef WITH_PYTHON
RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));

2
kernel/rtlil.h
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@ -1353,7 +1353,7 @@ public:
RTLIL::Module *module;
RTLIL::IdString name;
int width, start_offset, port_id;
bool port_input, port_output, upto;
bool port_input, port_output, upto, is_signed;
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);