Preserve 'signed'-ness of a verilog wire through RTLIL

As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser

frontends/ilang/ilang_parser.y

@@ -192,6 +192,9 @@ wire_options:
 	wire_options TOK_UPTO {
 		current_wire->upto = true;
 	} |
+	wire_options TOK_SIGNED {
+		current_wire->is_signed = true;
+	} |
 	wire_options TOK_OFFSET TOK_INT {
 		current_wire->start_offset = $3;
 	} |