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Preserve 'signed'-ness of a verilog wire through RTLIL

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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
This commit is contained in:
Vamsi K Vytla 2020-04-27 09:44:24 -07:00
parent 3eb24809a1
commit 5f9cd2e2f6
6 changed files with 13 additions and 1 deletions
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2
backends/ilang/ilang_backend.cc
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@ -131,6 +131,8 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
f << stringf("output %d ", wire->port_id);
if (wire->port_input && wire->port_output)
f << stringf("inout %d ", wire->port_id);
if (wire->is_signed)
f << stringf("signed ");
f << stringf("%s\n", wire->name.c_str());
}