From 5f84b8b3395c64e6a1927025a98ee12d7dc2e2ca Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Sat, 29 Nov 2025 15:32:19 -0800 Subject: [PATCH] Undo some other changes --- tests/functional/test_functional.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 24975fb51..6dc7909e5 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -40,12 +40,12 @@ def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): capture_output=True, check=False) raise -def test_cxx(name, cell, parameters, tmp_path, num_steps, rnd): +def test_cxx(cell, parameters, tmp_path, num_steps, rnd): rtlil_file = tmp_path / 'rtlil.il' vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc' cc_file = tmp_path / 'my_module_functional_cxx.cc' vcdharness_exe_file = tmp_path / 'a.out' - vcd_functional_file = tmp_path / f'{name}.vcd' + vcd_functional_file = tmp_path / 'functional.vcd' vcd_yosys_sim_file = tmp_path / 'yosys.vcd' cell.write_rtlil_file(rtlil_file, parameters) @@ -56,12 +56,12 @@ def test_cxx(name, cell, parameters, tmp_path, num_steps, rnd): yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) @pytest.mark.smt -def test_smt(name, cell, parameters, tmp_path, num_steps, rnd): +def test_smt(cell, parameters, tmp_path, num_steps, rnd): import smt_vcd rtlil_file = tmp_path / 'rtlil.il' smt_file = tmp_path / 'smtlib.smt' - vcd_functional_file = tmp_path / f'{name}.vcd' + vcd_functional_file = tmp_path / 'functional.vcd' vcd_yosys_sim_file = tmp_path / 'yosys.vcd' if hasattr(cell, 'smt_max_steps'): @@ -75,12 +75,12 @@ def test_smt(name, cell, parameters, tmp_path, num_steps, rnd): @pytest.mark.rkt @pytest.mark.parametrize("use_assoc_list_helpers", [True, False]) -def test_rkt(name, cell, parameters, tmp_path, num_steps, rnd, use_assoc_list_helpers): +def test_rkt(cell, parameters, tmp_path, num_steps, rnd): import rkt_vcd rtlil_file = tmp_path / 'rtlil.il' rkt_file = tmp_path / 'smtlib.rkt' - vcd_functional_file = tmp_path / f'{name}.vcd' + vcd_functional_file = tmp_path / 'functional.vcd' vcd_yosys_sim_file = tmp_path / 'yosys.vcd' cell.write_rtlil_file(rtlil_file, parameters)