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write_xaiger: holes PIs only if whitebox

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This commit is contained in:
Eddie Hung 2020-01-08 15:40:37 -08:00
parent 6e3e814025
commit 5f7349f26d
1 changed files with 18 additions and 13 deletions
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9
backends/aiger/xaiger.cc
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@ -626,9 +626,10 @@ struct XAigerWriter
if (box_module->has_processes()) if (box_module->has_processes())
Pass::call_on_module(module->design, box_module, "proc"); Pass::call_on_module(module->design, box_module, "proc");
bool whitebox = box_module->get_bool_attribute("\\whitebox");
auto r = cell_cache.insert(std::make_pair(derived_name, nullptr)); auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
Cell *holes_cell = r.first->second; Cell *holes_cell = r.first->second;
if (r.second && box_module->get_bool_attribute("\\whitebox")) { if (r.second && whitebox) {
holes_cell = holes_module->addCell(cell->name, cell->type); holes_cell = holes_module->addCell(cell->name, cell->type);
holes_cell->parameters = cell->parameters; holes_cell->parameters = cell->parameters;
r.first->second = holes_cell; r.first->second = holes_cell;
@ -641,7 +642,8 @@ struct XAigerWriter
RTLIL::Wire *holes_wire; RTLIL::Wire *holes_wire;
RTLIL::SigSpec port_sig; RTLIL::SigSpec port_sig;
if (w->port_input) if (w->port_input) {
if (whitebox)
for (int i = 0; i < GetSize(w); i++) { for (int i = 0; i < GetSize(w); i++) {
box_inputs++; box_inputs++;
holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
@ -654,6 +656,9 @@ struct XAigerWriter
if (holes_cell) if (holes_cell)
port_sig.append(holes_wire); port_sig.append(holes_wire);
} }
else
box_inputs += GetSize(w);
}
if (w->port_output) { if (w->port_output) {
box_outputs += GetSize(w); box_outputs += GetSize(w);
for (int i = 0; i < GetSize(w); i++) { for (int i = 0; i < GetSize(w); i++) {