Merge upstream yosys

tests/liberty/non-ascii.lib

@@ -0,0 +1,14 @@
+// The parser used to choke on the copyright symbol even in comments
+// © ® ø Φ
+library(dummy) {
+  cell(buffer) {
+    area : 1 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : "A" ;
+    }
+  }
+}

tests/liberty/non-ascii.lib.filtered.ok

@@ -0,0 +1,12 @@
+library(dummy) {
+  cell(buffer) {
+    area : 1 ;
+    pin(A) {
+      direction : input ;
+    }
+    pin(Y) {
+      direction : output ;
+      function : "A" ;
+    }
+  }
+}

tests/liberty/non-ascii.lib.verilogsim.ok

@@ -0,0 +1,5 @@
+module buffer (A, Y);
+  input A;
+  output Y;
+  assign Y = A; // "A"
+endmodule

tests/sat/share.v

@@ -30,3 +30,26 @@ module test_2(
 	end
 endmodule
 
+
+module test_3(
+	input [3:0] s,
+	input [7:0] a, b, c,
+	output reg [7:0] y0,
+	output reg [7:0] y1,
+	output reg [7:0] y2,
+	output reg [7:0] y3,
+);
+	wire is_onehot = s & (s - 1);
+
+	always @* begin
+		y0 <= 0;
+		y1 <= 0;
+		y2 <= 0;
+		y3 <= 0;
+		if (s < 3) y0 <= b / c;
+		if (3 <= s && s < 6) y1 <= c / b;
+		if (6 <= s && s < 9) y2 <= a / b;
+		if (9 <= s && s < 12) y3 <= b / a;
+	end
+endmodule
+

tests/sat/share.ys

@@ -3,11 +3,13 @@ proc;;
 
 copy test_1 gold_1
 copy test_2 gold_2
-share test_1 test_2;;
+copy test_3 gold_3
+share test_1 test_2 test_3;;
 
 select -assert-count 1 test_1/t:$mul
 select -assert-count 1 test_2/t:$mul
 select -assert-count 1 test_2/t:$div
+select -assert-count 1 test_3/t:$div
 
 miter -equiv -flatten -make_outputs -make_outcmp gold_1 test_1 miter_1
 sat -verify -prove trigger 0 -show-inputs -show-outputs miter_1
@@ -15,3 +17,5 @@ sat -verify -prove trigger 0 -show-inputs -show-outputs miter_1
 miter -equiv -flatten -make_outputs -make_outcmp gold_2 test_2 miter_2
 sat -verify -prove trigger 0 -show-inputs -show-outputs miter_2
 
+miter -equiv -flatten -make_outputs -make_outcmp gold_3 test_3 miter_3
+sat -verify -prove trigger 0 -show-inputs -show-outputs miter_3

tests/techmap/constmap.ys

@@ -0,0 +1,43 @@
+read_verilog << EOT
+
+module test();
+  wire [31:0] in;
+  wire [31:0] out;
+  assign out = in + 16;
+endmodule
+
+EOT
+
+constmap -cell const_cell O value
+select -assert-count 1 t:const_cell r:value=16 %i
+
+design -reset
+
+read_verilog -lib << EOT
+module const_cell(O);
+parameter value=0;
+output O;
+endmodule
+EOT
+
+read_verilog << EOT
+
+module test();
+  wire [31:0] in;
+  wire [31:0] out1;
+  wire [31:0] out2;
+  assign out1 = in + 16;
+  assign out2 = in + 32;
+endmodule
+
+EOT
+
+constmap -cell const_cell O value
+
+select -assert-count 2 t:const_cell
+select -assert-count 1 r:value=16
+select -assert-count 1 r:value=32
+select -assert-count 1 test/out1 %ci* r:value=16 %i
+select -assert-count 1 test/out2 %ci* r:value=32 %i
+select -assert-count 1 t:const_cell r:value=16 %i
+select -assert-count 1 t:const_cell r:value=32 %i

tests/various/.gitignore

@@ -1,6 +1,7 @@
 /*.log
 /*.out
 /aiger2*.aig
+/*.sel
 /write_gzip.v
 /write_gzip.v.gz
 /run-test.mk

tests/various/cutpoint_blackbox.ys

@@ -0,0 +1,72 @@
+read_verilog -specify << EOT
+module top(input a, b, output o);
+    wire c, d, e;
+    bb #(.SOME_PARAM(1)) bb1 (.a (a), .b (b), .o (c));
+    bb #(.SOME_PARAM(2)) bb2 (.a (a), .b (b), .o (d));
+    wb wb1 (.a (a), .b (b), .o (e));
+    some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
+endmodule
+
+(* blackbox *)
+module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
+assign o = a | b;
+specify
+	(a => o) = 1;
+endspecify
+endmodule
+
+(* whitebox *)
+module wb(input a, b, output o);
+assign o = a ^ b;
+endmodule
+
+module some_mod(input a, b, c, output o);
+assign o = a & (b | c);
+endmodule
+EOT
+
+hierarchy -top top
+design -save hier
+
+select -assert-none t:$anyseq
+select -assert-count 3 =t:?b
+cutpoint -blackbox
+
+select -assert-none =t:?b
+select -assert-none r:SOME_PARAM
+
+select -assert-count 3 t:$anyseq
+select -assert-count 3 t:$scopeinfo
+select -assert-count 3 t:$scopeinfo r:TYPE=blackbox %i
+select -assert-count 3 t:$scopeinfo n:*cutpoint.cc* %i
+
+# -noscopeinfo works with -blackbox
+design -load hier
+cutpoint -blackbox -noscopeinfo
+select -assert-none t:$scopeinfo
+
+# cutpoint -blackbox === cutpoint =A:whitebox =A:blackbox %u %C
+#                        (simplified to =A:*box %C)
+design -load hier
+cutpoint -blackbox
+rename -enumerate -pattern A_% t:$scopeinfo
+rename -enumerate -pattern B_% t:$anyseq
+rename -enumerate -pattern C_% w:*Anyseq*
+design -save gold
+select -write cutpoint.gold.sel =*
+
+design -load hier
+cutpoint =A:*box %C
+rename -enumerate -pattern A_% t:$scopeinfo
+rename -enumerate -pattern B_% t:$anyseq
+rename -enumerate -pattern C_% w:*Anyseq*
+design -save gate
+select -write cutpoint.gate.sel
+select -read cutpoint.gold.sel
+# nothing in gate but not gold
+select -assert-none % %n
+
+design -load gold
+select -read cutpoint.gate.sel
+# nothing in gold but not gate
+select -assert-none % %n

tests/various/stat.ys

@@ -1,4 +1,4 @@
-read_rtlil << EOF
+read_rtlil << EOT
 module \top
   wire input 1 \A
   wire output 2 \Y
@@ -8,7 +8,67 @@ module \top
     connect \Y \Y
   end
 end
-EOF
+EOT
 logger -expect log "Chip area for module '\\top': 9.072000" 1
 logger -expect-no-warnings
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
+
+
+design -reset
+read_rtlil << EOT
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  wire output 3 \N
+
+  cell \sg13g2_and2_1 \sub1
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+
+  cell \child \sequential
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \N \N
+  end
+
+  cell \child \sequential1
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \N \N
+  end
+
+  cell \sg13g2_and2_1 \sub2
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+
+module \child
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \R
+
+  wire output 4 \Y
+  wire output 5 \N
+
+  cell \sg13g2_dfrbp_1 \sequential_ff
+    connect \CLK \A
+    connect \D \B
+    connect \Q \Y
+    connect \Q_N \N
+    connect \RESET_B \R
+  end
+
+end
+EOT
+logger -expect log "Chip area for top module '\\top': 112.492800" 1
+logger -expect log "of which used for sequential elements: 94.348800" 1
+logger -expect-no-warnings
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top