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Updated changelog

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Miodrag Milanovic 2023-02-08 10:11:47 +01:00
parent 417fadbefd
commit 5f33c0e0b2
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18
CHANGELOG
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@ -4,7 +4,25 @@ List of major changes and improvements between releases
Yosys 0.25 .. Yosys 0.25-dev
--------------------------
* New commands and options
- Added "bwmuxmap" pass to replace $bwmux cells with equivalent logic.
- Added "xprop" pass for formal x propagation.
- Added "splitcells" pass to split up multi-bit cells.
- Added "viz" pass to visualize data flow graph.
- Added option "-make_cover" to "miter" pass.
- Added option "-noparallelcase" to "write_verilog" pass.
- Added option "-chain" to "insbuf" pass.
- Added options "-hierarchy" and "-assume" to "formalff" pass.
- Added options "-append" and "-summary" to "sim" pass.
- Added option "-ywmap" to "write_btor" pass.
- Added option "-ignore-self-reset" to "fsm_detect" pass.
* Verilog
- Support for struct members of union type.
- Support for struct member package types.
* Various
- Added Yosys witness (.yw) cosimulation.
- GCC 4.8 is deprecated, compiler with full C++11 support is required.
Yosys 0.24 .. Yosys 0.25

3
passes/techmap/bmuxmap.cc
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@ -33,6 +33,9 @@ struct BmuxmapPass : public Pass {
log("\n");
log("This pass transforms $bmux cells to trees of $mux cells.\n");
log("\n");
log(" -pmux\n");
log(" transform to $pmux instead of $mux cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{