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Tidy up

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This commit is contained in:
Eddie Hung 2019-04-22 17:47:05 -07:00
parent 8f30019b68
commit 5f30a8795d
2 changed files with 1 additions and 7 deletions
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2
frontends/aiger/aigerparse.cc
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@ -361,7 +361,7 @@ void AigerReader::parse_xaiger()
} }
} }
else if (c == 'r') { else if (c == 'r') {
uint32_t dataSize = parse_xaiger_literal(f); /*uint32_t dataSize =*/ parse_xaiger_literal(f);
uint32_t flopNum = parse_xaiger_literal(f); uint32_t flopNum = parse_xaiger_literal(f);
f.ignore(flopNum * sizeof(uint32_t)); f.ignore(flopNum * sizeof(uint32_t));
log_assert(inputs.size() >= flopNum); log_assert(inputs.size() >= flopNum);

6
passes/techmap/abc9.cc
View file

@ -561,11 +561,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
output_bits.insert({wire, i}); output_bits.insert({wire, i});
} }
else { else {
//if (w->name == "\\__dummy_o__") {
// log("Don't call ABC as there is nothing to map.\n");
// goto cleanup;
//}
// Attempt another wideports_split here because there // Attempt another wideports_split here because there
// exists the possibility that different bits of a port // exists the possibility that different bits of a port
// could be an input and output, therefore parse_xiager() // could be an input and output, therefore parse_xiager()
@ -935,7 +930,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// log("Don't call ABC as there is nothing to map.\n"); // log("Don't call ABC as there is nothing to map.\n");
//} //}
cleanup:
if (cleanup) if (cleanup)
{ {
log("Removing temp directory.\n"); log("Removing temp directory.\n");