mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Add automatic verific import in hierarchy command

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-20 23:45:01 +02:00
parent 626b555244
commit 5f2bc1ce76
3 changed files with 75 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

20
passes/hierarchy/hierarchy.cc
View file

@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
#include "frontends/verific/verific.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
@ -421,6 +422,7 @@ struct HierarchyPass : public Pass {
bool flag_simcheck = false;
bool purge_lib = false;
RTLIL::Module *top_mod = NULL;
std::string load_top_mod;
std::vector<std::string> libdirs;
bool auto_top_mode = false;
@ -511,7 +513,7 @@ struct HierarchyPass : public Pass {
top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
}
if (top_mod == NULL)
log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
load_top_mod = args[argidx];
continue;
}
if (args[argidx] == "-auto-top") {
@ -522,6 +524,22 @@ struct HierarchyPass : public Pass {
}
extra_args(args, argidx, design, false);
if (!load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) {
verific_import(design, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod));
}
#endif
if (top_mod == NULL)
log_cmd_error("Module `%s' not found!\n", load_top_mod.c_str());
} else {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending)
verific_import(design);
#endif
}
if (generate_mode) {
generate(design, generate_cells, generate_ports);
return;