mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-26 03:46:22 +00:00
Migrate build system to CMake
See #5895 for details. This commit does not include CI or documentation changes.
This commit is contained in:
Catherine
parent
7bcda9d304
commit
5f1d2297aa
207 changed files with 5257 additions and 2294 deletions
2
techlibs/.gitignore
vendored
2
techlibs/.gitignore
vendored
|
|
@ -1,2 +0,0 @@
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blackbox.v
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*_pm.h
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20
techlibs/CMakeLists.txt
Normal file
20
techlibs/CMakeLists.txt
Normal file
|
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@ -0,0 +1,20 @@
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add_subdirectory(achronix)
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add_subdirectory(analogdevices)
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add_subdirectory(anlogic)
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add_subdirectory(common)
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add_subdirectory(coolrunner2)
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add_subdirectory(easic)
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add_subdirectory(efinix)
|
||||
add_subdirectory(fabulous)
|
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add_subdirectory(gatemate)
|
||||
add_subdirectory(gowin)
|
||||
add_subdirectory(greenpak4)
|
||||
add_subdirectory(ice40)
|
||||
add_subdirectory(intel)
|
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add_subdirectory(intel_alm)
|
||||
add_subdirectory(lattice)
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add_subdirectory(microchip)
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add_subdirectory(nanoxplore)
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add_subdirectory(quicklogic)
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add_subdirectory(sf2)
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add_subdirectory(xilinx)
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28
techlibs/achronix/CMakeLists.txt
Normal file
28
techlibs/achronix/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,28 @@
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yosys_pass(synth_achronix
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synth_achronix.cc
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REQUIRES
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abc
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blackbox
|
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check
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clean
|
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deminout
|
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dfflegalize
|
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flatten
|
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hierarchy
|
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iopadmap
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memory_map
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opt
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proc
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read_verilog
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setundef
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stat
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synth
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techmap
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tribuf
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write_verilog
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DATA_DIR
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achronix
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DATA_FILES
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speedster22i/cells_sim.v
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speedster22i/cells_map.v
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)
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@ -1,6 +0,0 @@
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OBJS += techlibs/achronix/synth_achronix.o
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$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
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$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
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65
techlibs/analogdevices/CMakeLists.txt
Normal file
65
techlibs/analogdevices/CMakeLists.txt
Normal file
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@ -0,0 +1,65 @@
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yosys_pass(synth_analogdevices
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synth_analogdevices.cc
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REQUIRES
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abc
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alumacc
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blackbox
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check
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chtype
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clean
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delete
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deminout
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dfflegalize
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flatten
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fsm
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hierarchy
|
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iopadmap
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memory
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memory_dff
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memory_libmap
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memory_map
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muxcover
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muxpack
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opt
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opt_clean
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opt_expr
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opt_lut_ins
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peepopt
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pmux2shiftx
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proc
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read_verilog
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select
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setattr
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share
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simplemap
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stat
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techmap
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tribuf
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wreduce
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write_edif
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xilinx_dffopt
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xilinx_dsp
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xilinx_srl
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zinit
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DATA_DIR
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analogdevices
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DATA_FILES
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cells_map.v
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cells_sim.v
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lutrams.txt
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lutrams_map.v
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brams_defs.vh
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brams.txt
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brams_map.v
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arith_map.v
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ff_map.v
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lut_map.v
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mux_map.v
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dsp_map.v
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abc9_model.v
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)
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@ -1,21 +0,0 @@
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OBJS += techlibs/analogdevices/synth_analogdevices.o
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/cells_sim.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lutrams.txt))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lutrams_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/brams_defs.vh))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/brams.txt))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/brams_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/arith_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/ff_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/lut_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/mux_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/dsp_map.v))
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$(eval $(call add_share_file,share/analogdevices,techlibs/analogdevices/abc9_model.v))
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45
techlibs/anlogic/CMakeLists.txt
Normal file
45
techlibs/anlogic/CMakeLists.txt
Normal file
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@ -0,0 +1,45 @@
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yosys_pass(anlogic_eqn
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anlogic_eqn.cc
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)
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yosys_pass(anlogic_fixcarry
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anlogic_fixcarry.cc
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)
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yosys_pass(synth_anlogic
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synth_anlogic.cc
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REQUIRES
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abc
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anlogic_eqn
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anlogic_fixcarry
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blackbox
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check
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clean
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deminout
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dfflegalize
|
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flatten
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hierarchy
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memory_libmap
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memory_map
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opt
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opt_expr
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proc
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read_verilog
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simplemap
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stat
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synth
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techmap
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tribuf
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write_edif
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write_json
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DATA_DIR
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anlogic
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DATA_FILES
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cells_map.v
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arith_map.v
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cells_sim.v
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eagle_bb.v
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lutrams.txt
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lutrams_map.v
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brams.txt
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brams_map.v
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)
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@ -1,13 +0,0 @@
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OBJS += techlibs/anlogic/synth_anlogic.o
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OBJS += techlibs/anlogic/anlogic_eqn.o
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OBJS += techlibs/anlogic/anlogic_fixcarry.o
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))
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2
techlibs/common/.gitignore
vendored
2
techlibs/common/.gitignore
vendored
|
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@ -1,2 +0,0 @@
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simlib_help.inc
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simcells_help.inc
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87
techlibs/common/CMakeLists.txt
Normal file
87
techlibs/common/CMakeLists.txt
Normal file
|
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@ -0,0 +1,87 @@
|
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if (YOSYS_ENABLE_ABC)
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set(abc_requires abc abc9)
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endif()
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yosys_pass(synth
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synth.cc
|
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DEFINITIONS
|
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$<$<BOOL:${YOSYS_ENABLE_ABC}>:YOSYS_ENABLE_ABC>
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REQUIRES
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${abc_requires}
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alumacc
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arith_tree
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booth
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check
|
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clean
|
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flatten
|
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flowmap
|
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fsm
|
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hierarchy
|
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memory
|
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memory_map
|
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opt
|
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opt_clean
|
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opt_expr
|
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peepopt
|
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proc
|
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share
|
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stat
|
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techmap
|
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wreduce
|
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DATA_FILES
|
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simlib.v
|
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simcells.v
|
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techmap.v
|
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smtmap.v
|
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pmux2mux.v
|
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adff2dff.v
|
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dff2ff.v
|
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gate2lut.v
|
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cmp2lut.v
|
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mul2dsp.v
|
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abc9_model.v
|
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abc9_map.v
|
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abc9_unmap.v
|
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cmp2lcu.v
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cmp2softlogic.v
|
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|
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choices/kogge-stone.v
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choices/han-carlson.v
|
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choices/sklansky.v
|
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)
|
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|
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yosys_pass(prep
|
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prep.cc
|
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REQUIRES
|
||||
check
|
||||
flatten
|
||||
future
|
||||
hierarchy
|
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memory_collect
|
||||
memory_dff
|
||||
memory_memx
|
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opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
proc
|
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sort
|
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stat
|
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wreduce
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)
|
||||
|
||||
yosys_pass(opensta
|
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opensta.cc
|
||||
)
|
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|
||||
yosys_pass(sdc_expand
|
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sdc_expand.cc
|
||||
REQUIRES
|
||||
chtype
|
||||
design
|
||||
hierarchy
|
||||
icell_liberty
|
||||
memory
|
||||
opensta
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proc
|
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read_verilog
|
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write_verilog
|
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)
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|
|
@ -1,41 +0,0 @@
|
|||
|
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ifneq ($(SMALL),1)
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OBJS += techlibs/common/synth.o
|
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OBJS += techlibs/common/prep.o
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OBJS += techlibs/common/opensta.o
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OBJS += techlibs/common/sdc_expand.o
|
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endif
|
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|
||||
GENFILES += techlibs/common/simlib_help.inc
|
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GENFILES += techlibs/common/simcells_help.inc
|
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|
||||
techlibs/common/simlib_help.inc: techlibs/common/cellhelp.py techlibs/common/simlib.v
|
||||
$(Q) mkdir -p techlibs/common
|
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$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
|
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$(Q) mv $@.new $@
|
||||
|
||||
techlibs/common/simcells_help.inc: techlibs/common/cellhelp.py techlibs/common/simcells.v
|
||||
$(Q) mkdir -p techlibs/common
|
||||
$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
|
||||
$(Q) mv $@.new $@
|
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|
||||
kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc
|
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|
||||
$(eval $(call add_share_file,share,techlibs/common/simlib.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/simcells.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/techmap.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/smtmap.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
|
||||
$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
|
||||
$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v))
|
||||
$(eval $(call add_share_file,share/choices,techlibs/common/choices/sklansky.v))
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from __future__ import annotations
|
||||
import fileinput
|
||||
import json
|
||||
from pathlib import Path
|
||||
|
||||
class SimHelper:
|
||||
name: str = ""
|
||||
title: str = ""
|
||||
ports: str = ""
|
||||
source: str = ""
|
||||
desc: list[str]
|
||||
code: list[str]
|
||||
group: str = ""
|
||||
ver: str = "1"
|
||||
tags: list[str]
|
||||
|
||||
def __init__(self) -> None:
|
||||
self.desc = []
|
||||
self.tags = []
|
||||
|
||||
def __str__(self) -> str:
|
||||
printed_fields = [
|
||||
"name", "title", "ports", "source", "desc", "code", "group", "ver",
|
||||
"tags",
|
||||
]
|
||||
# generate C++ struct
|
||||
val = f"cell_help[{json.dumps(self.name)}] = "
|
||||
val += "{\n"
|
||||
for field in printed_fields:
|
||||
field_val = getattr(self, field)
|
||||
if isinstance(field_val, list):
|
||||
field_val = "\n".join(field_val)
|
||||
field_val = field_val.strip()
|
||||
val += f' {json.dumps(field_val)},\n'
|
||||
val += "};\n"
|
||||
return val
|
||||
|
||||
def simcells_reparse(cell: SimHelper):
|
||||
# cut manual signature
|
||||
cell.desc = cell.desc[3:]
|
||||
|
||||
# code-block truth table
|
||||
new_desc = []
|
||||
indent = ""
|
||||
for line in cell.desc:
|
||||
if line.startswith("Truth table:"):
|
||||
indent = " "
|
||||
new_desc.pop()
|
||||
new_desc.extend(["::", ""])
|
||||
new_desc.append(indent + line)
|
||||
cell.desc = new_desc
|
||||
|
||||
# set version
|
||||
cell.ver = "2a"
|
||||
|
||||
simHelper = SimHelper()
|
||||
|
||||
for line in fileinput.input():
|
||||
line = line.rstrip()
|
||||
# special comments
|
||||
if line.startswith("//-"):
|
||||
simHelper.desc.append(line[4:] if len(line) > 4 else "")
|
||||
elif line.startswith("//* "):
|
||||
_, key, val = line.split(maxsplit=2)
|
||||
setattr(simHelper, key, val)
|
||||
|
||||
# code parsing
|
||||
if line.startswith("module "):
|
||||
clean_line = line[7:].replace("\\", "").replace(";", "")
|
||||
simHelper.name, simHelper.ports = clean_line.split(maxsplit=1)
|
||||
simHelper.code = []
|
||||
short_filename = Path(fileinput.filename()).name
|
||||
simHelper.source = f'{short_filename}:{fileinput.filelineno()}'
|
||||
elif not line.startswith("endmodule"):
|
||||
line = " " + line
|
||||
try:
|
||||
simHelper.code.append(line.replace("\t", " "))
|
||||
except AttributeError:
|
||||
# no module definition, ignore line
|
||||
pass
|
||||
if line.startswith("endmodule"):
|
||||
short_filename = Path(fileinput.filename()).name
|
||||
if simHelper.ver == "1" and short_filename == "simcells.v":
|
||||
# default simcells parsing
|
||||
simcells_reparse(simHelper)
|
||||
|
||||
# check help
|
||||
if simHelper.desc and simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith(' '):
|
||||
simHelper.desc.pop(1)
|
||||
|
||||
# check group
|
||||
assert simHelper.group, f"techlibs/common/{simHelper.source}: {simHelper.name} cell missing group"
|
||||
|
||||
# dump
|
||||
print(simHelper)
|
||||
# new
|
||||
simHelper = SimHelper()
|
||||
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
#if !defined(YOSYS_DISABLE_SPAWN)
|
||||
#if defined(YOSYS_ENABLE_SPAWN)
|
||||
struct OpenstaPass : public Pass
|
||||
{
|
||||
OpenstaPass() : Pass("opensta", "run OpenSTA") { }
|
||||
|
|
|
|||
42
techlibs/coolrunner2/CMakeLists.txt
Normal file
42
techlibs/coolrunner2/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
yosys_pass(coolrunner2_sop
|
||||
coolrunner2_sop.cc
|
||||
)
|
||||
yosys_pass(coolrunner2_fixup
|
||||
coolrunner2_fixup.cc
|
||||
)
|
||||
|
||||
yosys_pass(synth_coolrunner2
|
||||
synth_coolrunner2.cc
|
||||
REQUIRES
|
||||
abc
|
||||
attrmvcp
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
coolrunner2_fixup
|
||||
coolrunner2_sop
|
||||
dffinit
|
||||
dfflibmap
|
||||
extract
|
||||
extract_counter
|
||||
flatten
|
||||
hierarchy
|
||||
iopadmap
|
||||
opt
|
||||
proc
|
||||
read_verilog
|
||||
splitnets
|
||||
stat
|
||||
synth
|
||||
techmap
|
||||
tribuf
|
||||
write_json
|
||||
DATA_DIR
|
||||
coolrunner2
|
||||
DATA_FILES
|
||||
cells_latch.v
|
||||
cells_sim.v
|
||||
cells_counter_map.v
|
||||
tff_extract.v
|
||||
xc2_dff.lib
|
||||
)
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
|
||||
OBJS += techlibs/coolrunner2/synth_coolrunner2.o
|
||||
OBJS += techlibs/coolrunner2/coolrunner2_sop.o
|
||||
OBJS += techlibs/coolrunner2/coolrunner2_fixup.o
|
||||
|
||||
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
|
||||
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_counter_map.v))
|
||||
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/tff_extract.v))
|
||||
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))
|
||||
19
techlibs/easic/CMakeLists.txt
Normal file
19
techlibs/easic/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
yosys_pass(synth_easic
|
||||
synth_easic.cc
|
||||
REQUIRES
|
||||
abc
|
||||
blackbox
|
||||
check
|
||||
dfflibmap
|
||||
flatten
|
||||
hierarchy
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
proc
|
||||
read_liberty
|
||||
stat
|
||||
synth
|
||||
techmap
|
||||
write_verilog
|
||||
)
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
|
||||
OBJS += techlibs/easic/synth_easic.o
|
||||
|
||||
40
techlibs/efinix/CMakeLists.txt
Normal file
40
techlibs/efinix/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
yosys_pass(efinix_fixcarry
|
||||
efinix_fixcarry.cc
|
||||
)
|
||||
|
||||
yosys_pass(synth_efinix
|
||||
synth_efinix.cc
|
||||
REQUIRES
|
||||
abc
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
efinix_fixcarry
|
||||
flatten
|
||||
hierarchy
|
||||
memory_libmap
|
||||
memory_map
|
||||
opt
|
||||
opt_expr
|
||||
proc
|
||||
read_verilog
|
||||
simplemap
|
||||
stat
|
||||
synth
|
||||
techmap
|
||||
tribuf
|
||||
write_edif
|
||||
write_json
|
||||
DATA_DIR
|
||||
efinix
|
||||
DATA_FILES
|
||||
cells_map.v
|
||||
arith_map.v
|
||||
cells_sim.v
|
||||
brams_map.v
|
||||
gbuf_map.v
|
||||
brams.txt
|
||||
)
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
|
||||
OBJS += techlibs/efinix/synth_efinix.o
|
||||
OBJS += techlibs/efinix/efinix_fixcarry.o
|
||||
|
||||
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
|
||||
$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
|
||||
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
|
||||
$(eval $(call add_share_file,share/efinix,techlibs/efinix/gbuf_map.v))
|
||||
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))
|
||||
41
techlibs/fabulous/CMakeLists.txt
Normal file
41
techlibs/fabulous/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
yosys_pass(synth_fabulous
|
||||
synth_fabulous.cc
|
||||
REQUIRES
|
||||
abc
|
||||
alumacc
|
||||
check
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_libmap
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
share
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_json
|
||||
DATA_DIR
|
||||
fabulous
|
||||
DATA_FILES
|
||||
cells_map.v
|
||||
prims.v
|
||||
latches_map.v
|
||||
ff_map.v
|
||||
ram_regfile.txt
|
||||
regfile_map.v
|
||||
io_map.v
|
||||
arith_map.v
|
||||
)
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
|
||||
OBJS += techlibs/fabulous/synth_fabulous.o
|
||||
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/cells_map.v))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/prims.v))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/latches_map.v))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
|
||||
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v))
|
||||
2
techlibs/gatemate/.gitignore
vendored
2
techlibs/gatemate/.gitignore
vendored
|
|
@ -1,4 +1,2 @@
|
|||
lut_tree_cells.genlib
|
||||
lut_tree_map.v
|
||||
lut_tree_lib.mk
|
||||
|
||||
|
|
|
|||
65
techlibs/gatemate/CMakeLists.txt
Normal file
65
techlibs/gatemate/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
yosys_pass(gatemate_foldinv
|
||||
gatemate_foldinv.cc
|
||||
)
|
||||
|
||||
add_custom_command(
|
||||
DEPENDS make_lut_tree_lib.py
|
||||
# yosys_pass(DATA_FILES) expects the files to be in the source directory
|
||||
OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/lut_tree_cells.genlib ${CMAKE_CURRENT_SOURCE_DIR}/lut_tree_map.v
|
||||
COMMAND ${Python3_EXECUTABLE} make_lut_tree_lib.py
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
VERBATIM
|
||||
)
|
||||
yosys_pass(synth_gatemate
|
||||
synth_gatemate.cc
|
||||
REQUIRES
|
||||
abc
|
||||
alumacc
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
gatemate_foldinv
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_libmap
|
||||
memory_map
|
||||
muxcover
|
||||
muxpack
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
share
|
||||
simplemap
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_json
|
||||
write_verilog
|
||||
DATA_DIR
|
||||
gatemate
|
||||
DATA_FILES
|
||||
reg_map.v
|
||||
mux_map.v
|
||||
lut_map.v
|
||||
mul_map.v
|
||||
arith_map.v
|
||||
cells_sim.v
|
||||
cells_bb.v
|
||||
brams_map.v
|
||||
brams.txt
|
||||
brams_init_20.vh
|
||||
brams_init_40.vh
|
||||
inv_map.v
|
||||
lut_tree_cells.genlib
|
||||
lut_tree_map.v
|
||||
)
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
|
||||
OBJS += techlibs/gatemate/synth_gatemate.o
|
||||
OBJS += techlibs/gatemate/gatemate_foldinv.o
|
||||
|
||||
GENFILES += techlibs/gatemate/lut_tree_cells.genlib
|
||||
GENFILES += techlibs/gatemate/lut_tree_map.v
|
||||
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/reg_map.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mux_map.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/lut_map.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mul_map.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/arith_map.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/cells_bb.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_map.v))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams.txt))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_20.vh))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_40.vh))
|
||||
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/inv_map.v))
|
||||
|
||||
EXTRA_OBJS += techlibs/gatemate/lut_tree_lib.mk
|
||||
.SECONDARY: techlibs/gatemate/lut_tree_lib.mk
|
||||
|
||||
techlibs/gatemate/lut_tree_lib.mk: techlibs/gatemate/make_lut_tree_lib.py
|
||||
$(Q) mkdir -p techlibs/gatemate
|
||||
$(P) $(PYTHON_EXECUTABLE) $<
|
||||
$(Q) touch $@
|
||||
|
||||
techlibs/gatemate/lut_tree_cells.genlib: techlibs/gatemate/lut_tree_lib.mk
|
||||
techlibs/gatemate/lut_tree_map.v: techlibs/gatemate/lut_tree_lib.mk
|
||||
|
||||
$(eval $(call add_gen_share_file,share/gatemate,techlibs/gatemate/lut_tree_cells.genlib))
|
||||
$(eval $(call add_gen_share_file,share/gatemate,techlibs/gatemate/lut_tree_map.v))
|
||||
|
||||
|
|
@ -185,7 +185,7 @@ for name, expr in base_cells:
|
|||
if name not in ("$__CC4_XX", "$__CC3_X"):
|
||||
cells.append([name + "_X", 12, XOR(E, expr)])
|
||||
|
||||
with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf:
|
||||
with open("lut_tree_cells.genlib", "w") as glf:
|
||||
def mkGate(name, cost, expr, max_load=9999, block_delay = 10, fanout_delay = 5):
|
||||
name = name.replace(" ", "")
|
||||
expr = expr.map()
|
||||
|
|
@ -280,7 +280,7 @@ lut_prims = {
|
|||
)
|
||||
}
|
||||
|
||||
with open("techlibs/gatemate/lut_tree_map.v", "w") as vf:
|
||||
with open("lut_tree_map.v", "w") as vf:
|
||||
# Non-automatic rules
|
||||
print("""
|
||||
module \\$__ZERO (output Y); assign Y = 1'b0; endmodule
|
||||
|
|
|
|||
55
techlibs/gowin/CMakeLists.txt
Normal file
55
techlibs/gowin/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
yosys_pass(synth_gowin
|
||||
synth_gowin.cc
|
||||
REQUIRES
|
||||
abc
|
||||
abc9
|
||||
alumacc
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
hilomap
|
||||
iopadmap
|
||||
memory
|
||||
memory_libmap
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
opt_lut_ins
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
setundef
|
||||
share
|
||||
simplemap
|
||||
sort
|
||||
splitnets
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_json
|
||||
write_verilog
|
||||
DATA_DIR
|
||||
gowin
|
||||
DATA_FILES
|
||||
cells_map.v
|
||||
cells_sim.v
|
||||
cells_latch.v
|
||||
cells_xtra_gw1n.v
|
||||
cells_xtra_gw2a.v
|
||||
cells_xtra_gw5a.v
|
||||
arith_map.v
|
||||
brams_map.v
|
||||
brams_map_gw5a.v
|
||||
brams.txt
|
||||
lutrams_map.v
|
||||
lutrams.txt
|
||||
dsp_map.v
|
||||
)
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
|
||||
OBJS += techlibs/gowin/synth_gowin.o
|
||||
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_latch.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw1n.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw2a.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw5a.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v))
|
||||
42
techlibs/greenpak4/CMakeLists.txt
Normal file
42
techlibs/greenpak4/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
yosys_pass(greenpak4_dffinv
|
||||
greenpak4_dffinv.cc
|
||||
)
|
||||
|
||||
yosys_pass(synth_greenpak4
|
||||
synth_greenpak4.cc
|
||||
REQUIRES
|
||||
abc
|
||||
attrmvcp
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
dffinit
|
||||
dfflibmap
|
||||
extract_counter
|
||||
flatten
|
||||
greenpak4_dffinv
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory_map
|
||||
nlutmap
|
||||
opt
|
||||
proc
|
||||
read_verilog
|
||||
shregmap
|
||||
stat
|
||||
synth
|
||||
techmap
|
||||
tribuf
|
||||
write_json
|
||||
DATA_DIR
|
||||
greenpak4
|
||||
DATA_FILES
|
||||
cells_blackbox.v
|
||||
cells_latch.v
|
||||
cells_map.v
|
||||
cells_sim.v
|
||||
cells_sim_ams.v
|
||||
cells_sim_digital.v
|
||||
cells_sim_wip.v
|
||||
gp_dff.lib
|
||||
)
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
|
||||
OBJS += techlibs/greenpak4/synth_greenpak4.o
|
||||
OBJS += techlibs/greenpak4/greenpak4_dffinv.o
|
||||
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_ams.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_digital.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_wip.v))
|
||||
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
|
||||
84
techlibs/ice40/CMakeLists.txt
Normal file
84
techlibs/ice40/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
yosys_pass(ice40_braminit
|
||||
ice40_braminit.cc
|
||||
)
|
||||
yosys_pass(ice40_opt
|
||||
ice40_opt.cc
|
||||
REQUIRES
|
||||
opt_expr
|
||||
opt_merge
|
||||
opt_dff
|
||||
opt_clean
|
||||
)
|
||||
pmgen_command(ice40_dsp
|
||||
ice40_dsp.pmg
|
||||
)
|
||||
yosys_pass(ice40_dsp
|
||||
ice40_dsp.cc
|
||||
${PMGEN_ice40_dsp_OUTPUT}
|
||||
)
|
||||
pmgen_command(ice40_wrapcarry
|
||||
ice40_wrapcarry.pmg
|
||||
)
|
||||
yosys_pass(ice40_wrapcarry
|
||||
ice40_wrapcarry.cc
|
||||
${PMGEN_ice40_wrapcarry_OUTPUT}
|
||||
)
|
||||
|
||||
yosys_pass(synth_ice40
|
||||
synth_ice40.cc
|
||||
REQUIRES
|
||||
abc
|
||||
abc9
|
||||
alumacc
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
chtype
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
flowmap
|
||||
fsm
|
||||
hierarchy
|
||||
ice40_braminit
|
||||
ice40_dsp
|
||||
ice40_opt
|
||||
ice40_wrapcarry
|
||||
memory
|
||||
memory_dff
|
||||
memory_libmap
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
opt_lut
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
select
|
||||
setattr
|
||||
share
|
||||
simplemap
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_edif
|
||||
write_json
|
||||
DATA_DIR
|
||||
ice40
|
||||
DATA_FILES
|
||||
arith_map.v
|
||||
cells_map.v
|
||||
ff_map.v
|
||||
cells_sim.v
|
||||
latches_map.v
|
||||
brams.txt
|
||||
brams_map.v
|
||||
spram.txt
|
||||
spram_map.v
|
||||
dsp_map.v
|
||||
abc9_model.v
|
||||
)
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
|
||||
OBJS += techlibs/ice40/synth_ice40.o
|
||||
OBJS += techlibs/ice40/ice40_braminit.o
|
||||
OBJS += techlibs/ice40/ice40_opt.o
|
||||
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/ff_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/spram.txt))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/spram_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
|
||||
|
||||
OBJS += techlibs/ice40/ice40_dsp.o
|
||||
GENFILES += techlibs/ice40/ice40_dsp_pm.h
|
||||
techlibs/ice40/ice40_dsp.o: techlibs/ice40/ice40_dsp_pm.h
|
||||
$(eval $(call add_extra_objs,techlibs/ice40/ice40_dsp_pm.h))
|
||||
|
||||
OBJS += techlibs/ice40/ice40_wrapcarry.o
|
||||
GENFILES += techlibs/ice40/ice40_wrapcarry_pm.h
|
||||
techlibs/ice40/ice40_wrapcarry.o: techlibs/ice40/ice40_wrapcarry_pm.h
|
||||
$(eval $(call add_extra_objs,techlibs/ice40/ice40_wrapcarry_pm.h))
|
||||
52
techlibs/intel/CMakeLists.txt
Normal file
52
techlibs/intel/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
yosys_pass(synth_intel
|
||||
synth_intel.cc
|
||||
REQUIRES
|
||||
abc
|
||||
abc9
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_bram
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
setundef
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_verilog
|
||||
DATA_DIR
|
||||
intel
|
||||
DATA_FILES
|
||||
common/m9k_bb.v
|
||||
common/altpll_bb.v
|
||||
common/brams_m9k.txt
|
||||
common/brams_map_m9k.v
|
||||
common/ff_map.v
|
||||
|
||||
max10/cells_sim.v
|
||||
max10/cells_map.v
|
||||
|
||||
cyclone10lp/cells_sim.v
|
||||
cyclone10lp/cells_map.v
|
||||
|
||||
cycloneiv/cells_sim.v
|
||||
cycloneiv/cells_map.v
|
||||
|
||||
cycloneive/cells_sim.v
|
||||
cycloneive/cells_map.v
|
||||
)
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
|
||||
OBJS += techlibs/intel/synth_intel.o
|
||||
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
|
||||
|
||||
# Add the cell models and mappings for the VQM backend
|
||||
families := max10 cyclone10lp cycloneiv cycloneive
|
||||
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
|
||||
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
|
||||
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
|
||||
57
techlibs/intel_alm/CMakeLists.txt
Normal file
57
techlibs/intel_alm/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
yosys_pass(synth_intel_alm
|
||||
synth_intel_alm.cc
|
||||
REQUIRES
|
||||
abc9
|
||||
alumacc
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_bram
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
share
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
DATA_DIR
|
||||
intel_alm
|
||||
DATA_FILES
|
||||
# Techmap
|
||||
common/abc9_map.v
|
||||
common/abc9_unmap.v
|
||||
common/abc9_model.v
|
||||
common/alm_map.v
|
||||
common/alm_sim.v
|
||||
common/arith_alm_map.v
|
||||
common/dff_map.v
|
||||
common/dff_sim.v
|
||||
common/dsp_sim.v
|
||||
common/dsp_map.v
|
||||
common/mem_sim.v
|
||||
common/misc_sim.v
|
||||
|
||||
cyclonev/cells_sim.v
|
||||
|
||||
# RAM
|
||||
common/bram_m10k.txt
|
||||
common/bram_m10k_map.v
|
||||
common/lutram_mlab.txt
|
||||
|
||||
# Miscellaneous
|
||||
common/megafunction_bb.v
|
||||
)
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
|
||||
OBJS += techlibs/intel_alm/synth_intel_alm.o
|
||||
|
||||
# Techmap
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_map.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_unmap.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_model.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_map.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_sim.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_sim.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/misc_sim.v))
|
||||
|
||||
$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
|
||||
|
||||
# RAM
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
|
||||
|
||||
# Miscellaneous
|
||||
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
|
||||
92
techlibs/lattice/CMakeLists.txt
Normal file
92
techlibs/lattice/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
yosys_pass(lattice_gsr
|
||||
lattice_gsr.cc
|
||||
)
|
||||
|
||||
yosys_pass(synth_lattice
|
||||
synth_lattice.cc
|
||||
REQUIRES
|
||||
abc
|
||||
abc9
|
||||
alumacc
|
||||
attrmvcp
|
||||
autoname
|
||||
blackbox
|
||||
booth
|
||||
check
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
lattice_gsr
|
||||
memory
|
||||
memory_libmap
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
opt_lut_ins
|
||||
opt_merge
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
share
|
||||
simplemap
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_edif
|
||||
write_json
|
||||
zinit
|
||||
DATA_EXPLICIT
|
||||
lattice/cells_ff.vh cells_ff.vh
|
||||
lattice/cells_io.vh cells_io.vh
|
||||
lattice/cells_map_trellis.v cells_map_trellis.v
|
||||
lattice/cells_map_nexus.v cells_map_nexus.v
|
||||
lattice/common_sim.vh common_sim.vh
|
||||
lattice/parse_init.vh parse_init.vh
|
||||
lattice/ccu2d_sim.vh ccu2d_sim.vh
|
||||
lattice/ccu2c_sim.vh ccu2c_sim.vh
|
||||
lattice/cells_sim_ecp5.v cells_sim_ecp5.v
|
||||
lattice/cells_sim_xo2.v cells_sim_xo2.v
|
||||
lattice/cells_sim_xo3.v cells_sim_xo3.v
|
||||
lattice/cells_sim_xo3d.v cells_sim_xo3d.v
|
||||
lattice/cells_sim_nexus.v cells_sim_nexus.v
|
||||
lattice/cells_bb_ecp5.v cells_bb_ecp5.v
|
||||
lattice/cells_bb_xo2.v cells_bb_xo2.v
|
||||
lattice/cells_bb_xo3.v cells_bb_xo3.v
|
||||
lattice/cells_bb_xo3d.v cells_bb_xo3d.v
|
||||
lattice/cells_bb_nexus.v cells_bb_nexus.v
|
||||
lattice/lutrams_map_trellis.v lutrams_map_trellis.v
|
||||
lattice/lutrams_trellis.txt lutrams_trellis.txt
|
||||
lattice/lutrams_map_nexus.v lutrams_map_nexus.v
|
||||
lattice/lutrams_nexus.txt lutrams_nexus.txt
|
||||
lattice/lrams_map_nexus.v lrams_map_nexus.v
|
||||
lattice/lrams_nexus.txt lrams_nexus.txt
|
||||
lattice/brams_map_16kd.v brams_map_16kd.v
|
||||
lattice/brams_16kd.txt brams_16kd.txt
|
||||
lattice/brams_map_8kc.v brams_map_8kc.v
|
||||
lattice/brams_8kc.txt brams_8kc.txt
|
||||
lattice/brams_map_nexus.v brams_map_nexus.v
|
||||
lattice/brams_nexus.txt brams_nexus.txt
|
||||
lattice/arith_map_ccu2c.v arith_map_ccu2c.v
|
||||
lattice/arith_map_ccu2d.v arith_map_ccu2d.v
|
||||
lattice/arith_map_nexus.v arith_map_nexus.v
|
||||
lattice/latches_map.v latches_map.v
|
||||
lattice/dsp_map_18x18.v dsp_map_18x18.v
|
||||
lattice/dsp_map_nexus.v dsp_map_nexus.v
|
||||
|
||||
ecp5/cells_ff.vh cells_ff.vh
|
||||
ecp5/cells_io.vh cells_io.vh
|
||||
ecp5/common_sim.vh common_sim.vh
|
||||
ecp5/ccu2c_sim.vh ccu2c_sim.vh
|
||||
ecp5/cells_sim.v cells_sim_ecp5.v
|
||||
ecp5/cells_bb.v cells_bb_ecp5.v
|
||||
|
||||
nexus/parse_init.vh parse_init.vh
|
||||
nexus/cells_sim.v cells_sim_nexus.v
|
||||
nexus/cells_xtra.v cells_bb_nexus.v
|
||||
)
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
|
||||
OBJS += techlibs/lattice/synth_lattice.o
|
||||
OBJS += techlibs/lattice/lattice_gsr.o
|
||||
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map_trellis.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/parse_init.vh))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3d.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map_trellis.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_trellis.txt))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_nexus.txt))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lrams_map_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lrams_nexus.txt))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_nexus.txt))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_nexus.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
|
||||
$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_nexus.v))
|
||||
|
||||
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_ff.vh))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_io.vh))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/common_sim.vh))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/ccu2c_sim.vh))
|
||||
$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_sim_ecp5.v,cells_sim.v))
|
||||
$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_bb_ecp5.v,cells_bb.v))
|
||||
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/lattice/parse_init.vh))
|
||||
$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_sim_nexus.v,cells_sim.v))
|
||||
$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_bb_nexus.v,cells_xtra.v))
|
||||
76
techlibs/microchip/CMakeLists.txt
Normal file
76
techlibs/microchip/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
pmgen_command(microchip_dsp
|
||||
microchip_dsp.pmg
|
||||
)
|
||||
pmgen_command(microchip_dsp_cascade
|
||||
microchip_dsp_cascade.pmg
|
||||
)
|
||||
pmgen_command(microchip_dsp_CREG
|
||||
microchip_dsp_CREG.pmg
|
||||
)
|
||||
yosys_pass(microchip_dffopt
|
||||
microchip_dffopt.cc
|
||||
)
|
||||
yosys_pass(microchip_dsp
|
||||
microchip_dsp.cc
|
||||
${PMGEN_microchip_dsp_OUTPUT}
|
||||
${PMGEN_microchip_dsp_cascade_OUTPUT}
|
||||
${PMGEN_microchip_dsp_CREG_OUTPUT}
|
||||
)
|
||||
|
||||
yosys_pass(synth_microchip
|
||||
synth_microchip.cc
|
||||
REQUIRES
|
||||
abc
|
||||
alumacc
|
||||
attrmap
|
||||
blackbox
|
||||
check
|
||||
chtype
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
extract_reduce
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_dff
|
||||
memory_libmap
|
||||
memory_map
|
||||
microchip_dffopt
|
||||
microchip_dsp
|
||||
muxcover
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
select
|
||||
setattr
|
||||
share
|
||||
simplemap
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_edif
|
||||
write_verilog
|
||||
zinit
|
||||
DATA_DIR
|
||||
microchip
|
||||
DATA_FILES
|
||||
arith_map.v
|
||||
cells_map.v
|
||||
cells_sim.v
|
||||
polarfire_dsp_map.v
|
||||
|
||||
brams_defs.vh
|
||||
LSRAM_map.v
|
||||
LSRAM.txt
|
||||
uSRAM_map.v
|
||||
uSRAM.txt
|
||||
)
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
# ISC License
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
|
||||
|
||||
|
||||
OBJS += techlibs/microchip/synth_microchip.o
|
||||
OBJS += techlibs/microchip/microchip_dffopt.o
|
||||
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/polarfire_dsp_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
|
||||
|
||||
OBJS += techlibs/microchip/microchip_dsp.o
|
||||
GENFILES += techlibs/microchip/microchip_dsp_pm.h
|
||||
GENFILES += techlibs/microchip/microchip_dsp_CREG_pm.h
|
||||
GENFILES += techlibs/microchip/microchip_dsp_cascade_pm.h
|
||||
techlibs/microchip/microchip_dsp.o: techlibs/microchip/microchip_dsp_pm.h techlibs/microchip/microchip_dsp_CREG_pm.h techlibs/microchip/microchip_dsp_cascade_pm.h
|
||||
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_pm.h))
|
||||
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_CREG_pm.h))
|
||||
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_cascade_pm.h))
|
||||
68
techlibs/nanoxplore/CMakeLists.txt
Normal file
68
techlibs/nanoxplore/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
yosys_pass(nx_carry
|
||||
nx_carry.cc
|
||||
)
|
||||
|
||||
yosys_pass(synth_nanoxplore
|
||||
synth_nanoxplore.cc
|
||||
REQUIRES
|
||||
abc
|
||||
alumacc
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_libmap
|
||||
memory_map
|
||||
nx_carry
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
opt_merge
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
setundef
|
||||
share
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_json
|
||||
DATA_DIR
|
||||
nanoxplore
|
||||
DATA_FILES
|
||||
# Techmap
|
||||
arith_map.v
|
||||
brams_init.vh
|
||||
brams_map.v
|
||||
brams.txt
|
||||
cells_bb.v
|
||||
cells_bb_l.v
|
||||
cells_bb_m.v
|
||||
cells_bb_u.v
|
||||
cells_map.v
|
||||
cells_sim.v
|
||||
cells_sim_l.v
|
||||
cells_sim_m.v
|
||||
cells_sim_u.v
|
||||
cells_wrap.v
|
||||
cells_wrap_l.v
|
||||
cells_wrap_m.v
|
||||
cells_wrap_u.v
|
||||
io_map.v
|
||||
latches_map.v
|
||||
rf_init.vh
|
||||
rf_rams_l.txt
|
||||
rf_rams_m.txt
|
||||
rf_rams_u.txt
|
||||
rf_rams_map_l.v
|
||||
rf_rams_map_m.v
|
||||
rf_rams_map_u.v
|
||||
)
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
|
||||
OBJS += techlibs/nanoxplore/synth_nanoxplore.o
|
||||
OBJS += techlibs/nanoxplore/nx_carry.o
|
||||
|
||||
# Techmap
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_l.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_m.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_u.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_init.vh))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_l.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_m.v))
|
||||
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))
|
||||
1
techlibs/quicklogic/.gitignore
vendored
1
techlibs/quicklogic/.gitignore
vendored
|
|
@ -1 +0,0 @@
|
|||
/*_pm.h
|
||||
104
techlibs/quicklogic/CMakeLists.txt
Normal file
104
techlibs/quicklogic/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
yosys_pass(ql_bram_merge
|
||||
ql_bram_merge.cc
|
||||
)
|
||||
yosys_pass(ql_bram_types
|
||||
ql_bram_types.cc
|
||||
)
|
||||
pmgen_command(ql_dsp_macc
|
||||
ql_dsp_macc.pmg
|
||||
)
|
||||
yosys_pass(ql_dsp_macc
|
||||
ql_dsp_macc.cc
|
||||
${PMGEN_ql_dsp_macc_OUTPUT}
|
||||
)
|
||||
yosys_pass(ql_dsp_simd
|
||||
ql_dsp_simd.cc
|
||||
)
|
||||
yosys_pass(ql_dsp_io_regs
|
||||
ql_dsp_io_regs.cc
|
||||
)
|
||||
yosys_pass(ql_ioff
|
||||
ql_ioff.cc
|
||||
)
|
||||
|
||||
add_custom_command(
|
||||
DEPENDS qlf_k6n10f/generate_bram_types_sim.py
|
||||
# yosys_pass(DATA_FILES) expects the files to be in the source directory
|
||||
OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/bram_types_sim.v
|
||||
COMMAND ${Python3_EXECUTABLE} qlf_k6n10f/generate_bram_types_sim.py qlf_k6n10f/bram_types_sim.v
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
VERBATIM
|
||||
)
|
||||
yosys_pass(synth_quicklogic
|
||||
synth_quicklogic.cc
|
||||
REQUIRES
|
||||
abc9
|
||||
alumacc
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
chtype
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_libmap
|
||||
memory_map
|
||||
muxcover
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
opt_lut
|
||||
peepopt
|
||||
pmuxtree
|
||||
proc
|
||||
ql_bram_merge
|
||||
ql_bram_types
|
||||
ql_dsp_io_regs
|
||||
ql_dsp_macc
|
||||
ql_dsp_simd
|
||||
ql_ioff
|
||||
read_verilog
|
||||
setundef
|
||||
share
|
||||
shregmap
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_verilog
|
||||
DATA_DIR
|
||||
quicklogic
|
||||
DATA_FILES
|
||||
common/cells_sim.v
|
||||
|
||||
pp3/ffs_map.v
|
||||
pp3/lut_map.v
|
||||
pp3/latches_map.v
|
||||
pp3/cells_map.v
|
||||
pp3/cells_sim.v
|
||||
pp3/abc9_model.v
|
||||
pp3/abc9_map.v
|
||||
pp3/abc9_unmap.v
|
||||
|
||||
qlf_k6n10f/arith_map.v
|
||||
qlf_k6n10f/libmap_brams.txt
|
||||
qlf_k6n10f/libmap_brams_map.v
|
||||
qlf_k6n10f/brams_map.v
|
||||
qlf_k6n10f/brams_sim.v
|
||||
qlf_k6n10f/bram_types_sim.v
|
||||
qlf_k6n10f/cells_sim.v
|
||||
qlf_k6n10f/ffs_map.v
|
||||
qlf_k6n10f/dsp_sim.v
|
||||
qlf_k6n10f/dsp_map.v
|
||||
qlf_k6n10f/dsp_final_map.v
|
||||
qlf_k6n10f/TDP18K_FIFO.v
|
||||
qlf_k6n10f/ufifo_ctl.v
|
||||
qlf_k6n10f/sram1024x18_mem.v
|
||||
)
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
|
||||
$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ $@
|
||||
|
||||
OBJS += techlibs/quicklogic/synth_quicklogic.o
|
||||
OBJS += techlibs/quicklogic/ql_bram_merge.o
|
||||
OBJS += techlibs/quicklogic/ql_bram_types.o
|
||||
OBJS += techlibs/quicklogic/ql_dsp_simd.o
|
||||
OBJS += techlibs/quicklogic/ql_dsp_io_regs.o
|
||||
OBJS += techlibs/quicklogic/ql_ioff.o
|
||||
|
||||
# --------------------------------------
|
||||
|
||||
OBJS += techlibs/quicklogic/ql_dsp_macc.o
|
||||
GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v
|
||||
techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h
|
||||
$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h))
|
||||
|
||||
# --------------------------------------
|
||||
|
||||
$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
|
||||
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))
|
||||
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v))
|
||||
$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v))
|
||||
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v))
|
||||
34
techlibs/sf2/CMakeLists.txt
Normal file
34
techlibs/sf2/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
yosys_pass(synth_sf2
|
||||
synth_sf2.cc
|
||||
REQUIRES
|
||||
abc
|
||||
attrmap
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory_map
|
||||
opt
|
||||
opt_expr
|
||||
proc
|
||||
read_verilog
|
||||
simplemap
|
||||
stat
|
||||
synth
|
||||
techmap
|
||||
tribuf
|
||||
write_edif
|
||||
write_json
|
||||
write_verilog
|
||||
DATA_DIR
|
||||
sf2
|
||||
DATA_FILES
|
||||
arith_map.v
|
||||
cells_map.v
|
||||
cells_sim.v
|
||||
)
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
|
||||
OBJS += techlibs/sf2/synth_sf2.o
|
||||
|
||||
$(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v))
|
||||
$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v))
|
||||
$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_sim.v))
|
||||
|
||||
125
techlibs/xilinx/CMakeLists.txt
Normal file
125
techlibs/xilinx/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
yosys_pass(xilinx_dffopt
|
||||
xilinx_dffopt.cc
|
||||
)
|
||||
pmgen_command(xilinx_dsp
|
||||
xilinx_dsp.pmg
|
||||
)
|
||||
pmgen_command(xilinx_dsp48a
|
||||
xilinx_dsp48a.pmg
|
||||
)
|
||||
pmgen_command(xilinx_dsp_CREG
|
||||
xilinx_dsp_CREG.pmg
|
||||
)
|
||||
pmgen_command(xilinx_dsp_cascade
|
||||
xilinx_dsp_cascade.pmg
|
||||
)
|
||||
yosys_pass(xilinx_dsp
|
||||
xilinx_dsp.cc
|
||||
${PMGEN_xilinx_dsp_OUTPUT}
|
||||
${PMGEN_xilinx_dsp48a_OUTPUT}
|
||||
${PMGEN_xilinx_dsp_CREG_OUTPUT}
|
||||
${PMGEN_xilinx_dsp_cascade_OUTPUT}
|
||||
)
|
||||
pmgen_command(xilinx_srl
|
||||
xilinx_srl.pmg
|
||||
)
|
||||
yosys_pass(xilinx_srl
|
||||
xilinx_srl.cc
|
||||
${PMGEN_xilinx_srl_OUTPUT}
|
||||
)
|
||||
|
||||
yosys_pass(synth_xilinx
|
||||
synth_xilinx.cc
|
||||
REQUIRES
|
||||
abc
|
||||
alumacc
|
||||
blackbox
|
||||
check
|
||||
chtype
|
||||
clean
|
||||
clkbufmap
|
||||
deminout
|
||||
dfflegalize
|
||||
extractinv
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_dff
|
||||
memory_libmap
|
||||
memory_map
|
||||
muxcover
|
||||
muxpack
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
opt_lut_ins
|
||||
peepopt
|
||||
pmux2shiftx
|
||||
proc
|
||||
read_verilog
|
||||
select
|
||||
setattr
|
||||
share
|
||||
simplemap
|
||||
sort
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_edif
|
||||
write_json
|
||||
xilinx_dffopt
|
||||
xilinx_dsp
|
||||
xilinx_srl
|
||||
zinit
|
||||
DATA_DIR
|
||||
xilinx
|
||||
DATA_FILES
|
||||
cells_map.v
|
||||
cells_sim.v
|
||||
cells_xtra.v
|
||||
|
||||
lutrams_xcv.txt
|
||||
lutrams_xcv_map.v
|
||||
|
||||
lutrams_xc5v.txt
|
||||
lutrams_xcu.txt
|
||||
lutrams_xc5v_map.v
|
||||
|
||||
brams_xcv.txt
|
||||
brams_xcv_map.v
|
||||
|
||||
brams_defs.vh
|
||||
|
||||
brams_xc2v.txt
|
||||
brams_xc2v_map.v
|
||||
|
||||
brams_xc3sda.txt
|
||||
brams_xc3sda_map.v
|
||||
|
||||
brams_xc4v.txt
|
||||
brams_xc4v_map.v
|
||||
brams_xc5v_map.v
|
||||
brams_xc6v_map.v
|
||||
brams_xcu_map.v
|
||||
|
||||
urams.txt
|
||||
urams_map.v
|
||||
|
||||
arith_map.v
|
||||
ff_map.v
|
||||
lut_map.v
|
||||
mux_map.v
|
||||
xc3s_mult_map.v
|
||||
xc3sda_dsp_map.v
|
||||
xc6s_dsp_map.v
|
||||
xc4v_dsp_map.v
|
||||
xc5v_dsp_map.v
|
||||
xc7_dsp_map.v
|
||||
xcu_dsp_map.v
|
||||
|
||||
abc9_model.v
|
||||
)
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
|
||||
OBJS += techlibs/xilinx/synth_xilinx.o
|
||||
OBJS += techlibs/xilinx/xilinx_dffopt.o
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcu.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_defs.vh))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc5v_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc6v_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcu_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
|
||||
|
||||
OBJS += techlibs/xilinx/xilinx_dsp.o
|
||||
GENFILES += techlibs/xilinx/xilinx_dsp_pm.h
|
||||
GENFILES += techlibs/xilinx/xilinx_dsp48a_pm.h
|
||||
GENFILES += techlibs/xilinx/xilinx_dsp_CREG_pm.h
|
||||
GENFILES += techlibs/xilinx/xilinx_dsp_cascade_pm.h
|
||||
techlibs/xilinx/xilinx_dsp.o: techlibs/xilinx/xilinx_dsp_pm.h techlibs/xilinx/xilinx_dsp48a_pm.h techlibs/xilinx/xilinx_dsp_CREG_pm.h techlibs/xilinx/xilinx_dsp_cascade_pm.h
|
||||
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_pm.h))
|
||||
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp48a_pm.h))
|
||||
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_CREG_pm.h))
|
||||
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_cascade_pm.h))
|
||||
|
||||
OBJS += techlibs/xilinx/xilinx_srl.o
|
||||
GENFILES += techlibs/xilinx/xilinx_srl_pm.h
|
||||
techlibs/xilinx/xilinx_srl.o: techlibs/xilinx/xilinx_srl_pm.h
|
||||
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_srl_pm.h))
|
||||
Loading…
Add table
Add a link
Reference in a new issue