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Add $live and $fair cell types, add support for s_eventually keyword

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Clifford Wolf 2017-02-25 10:36:39 +01:00
parent 7af9727f78
commit 5f1d0b1024
14 changed files with 80 additions and 10 deletions
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frontends/verilog/verilog_lexer.l
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@ -191,6 +191,9 @@ YOSYS_NAMESPACE_END
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }