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Use singular for disabling of DRAM or BRAM inference.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-03-01 14:35:14 -08:00
parent eccaf101d8
commit 5ebeca12eb
2 changed files with 19 additions and 26 deletions
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19
manual/command-reference-manual.tex
View file

@ -4244,15 +4244,9 @@ compatible with 7-Series Xilinx devices.
is omitted if this parameter is not specified. is omitted if this parameter is not specified.
-vpr -vpr
generate an output netlist (and BLIF file) suitable for VPR. generate an output netlist (and BLIF file) suitable for VPR
(this feature is experimental and incomplete) (this feature is experimental and incomplete)
-nobrams
disable infering of block rams
-nodrams
disable infering of distributed rams
-run <from_label>:<to_label> -run <from_label>:<to_label>
only run the commands between the labels (see below). an empty only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is from label is synonymous to 'begin', and empty to label is
@ -4280,11 +4274,11 @@ The following commands are executed by this synthesis command:
coarse: coarse:
synth -run coarse synth -run coarse
bram: (only executed when '-nobrams' is not given) bram:
memory_bram -rules +/xilinx/brams.txt memory_bram -rules +/xilinx/brams.txt
techmap -map +/xilinx/brams_map.v techmap -map +/xilinx/brams_map.v
dram: (only executed when '-nodrams' is not given) dram:
memory_bram -rules +/xilinx/drams.txt memory_bram -rules +/xilinx/drams.txt
techmap -map +/xilinx/drams_map.v techmap -map +/xilinx/drams_map.v
@ -4294,17 +4288,16 @@ The following commands are executed by this synthesis command:
dffsr2dff dffsr2dff
dff2dffe dff2dffe
opt -full opt -full
techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v techmap -map +/techmap.v -map +/xilinx/arith_map.v
opt -fast opt -fast
map_luts: map_luts:
abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!) abc -luts 2:2,3,6:5,10,20 [-dff]
abc -lut 5 [-dff] (with '-vpr' only!)
clean clean
map_cells: map_cells:
techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode) techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)
dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
clean clean
check: check:

26
techlibs/xilinx/synth_xilinx.cc
View file

@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass
log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n"); log(" (this feature is experimental and incomplete)\n");
log("\n"); log("\n");
log(" -nobrams\n"); log(" -nobram\n");
log(" disable infering of block rams\n"); log(" disable infering of block rams\n");
log("\n"); log("\n");
log(" -nodrams\n"); log(" -nodram\n");
log(" disable infering of distributed rams\n"); log(" disable infering of distributed rams\n");
log("\n"); log("\n");
log(" -run <from_label>:<to_label>\n"); log(" -run <from_label>:<to_label>\n");
@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass
log(" coarse:\n"); log(" coarse:\n");
log(" synth -run coarse\n"); log(" synth -run coarse\n");
log("\n"); log("\n");
log(" bram: (only executed when '-nobrams' is not given)\n"); log(" bram: (only executed when '-nobram' is not given)\n");
log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" memory_bram -rules +/xilinx/brams.txt\n");
log(" techmap -map +/xilinx/brams_map.v\n"); log(" techmap -map +/xilinx/brams_map.v\n");
log("\n"); log("\n");
log(" dram: (only executed when '-nodrams' is not given)\n"); log(" dram: (only executed when '-nodram' is not given)\n");
log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" memory_bram -rules +/xilinx/drams.txt\n");
log(" techmap -map +/xilinx/drams_map.v\n"); log(" techmap -map +/xilinx/drams_map.v\n");
log("\n"); log("\n");
@ -144,8 +144,8 @@ struct SynthXilinxPass : public Pass
bool flatten = false; bool flatten = false;
bool retime = false; bool retime = false;
bool vpr = false; bool vpr = false;
bool noBrams = false; bool nobram = false;
bool noDrams = false; bool nodram = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -182,12 +182,12 @@ struct SynthXilinxPass : public Pass
vpr = true; vpr = true;
continue; continue;
} }
if (args[argidx] == "-nobrams") { if (args[argidx] == "-nobram") {
noBrams = true; nobram = true;
continue; continue;
} }
if (args[argidx] == "-nodrams") { if (args[argidx] == "-nodram") {
noDrams = true; nodram = true;
continue; continue;
} }
break; break;
@ -212,7 +212,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
if (!noBrams) { if (!nobram) {
Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
} }
@ -232,7 +232,7 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "bram")) if (check_label(active, run_from, run_to, "bram"))
{ {
if (!noBrams) { if (!nobram) {
Pass::call(design, "memory_bram -rules +/xilinx/brams.txt"); Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
Pass::call(design, "techmap -map +/xilinx/brams_map.v"); Pass::call(design, "techmap -map +/xilinx/brams_map.v");
} }
@ -240,7 +240,7 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "dram")) if (check_label(active, run_from, run_to, "dram"))
{ {
if (!noDrams) { if (!nodram) {
Pass::call(design, "memory_bram -rules +/xilinx/drams.txt"); Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
Pass::call(design, "techmap -map +/xilinx/drams_map.v"); Pass::call(design, "techmap -map +/xilinx/drams_map.v");
} }