Undo Liberty stuff

Makefile

@@ -949,7 +949,6 @@ endif
 	+cd tests/fmt && bash run-test.sh
 	# +cd tests/cxxrtl && bash run-test.sh
 	+cd tests/liberty && bash run-test.sh
-	+cd tests/liberty_verilog && bash run-test.sh
 ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
 	+cd tests/functional && bash run-test.sh
 endif

frontends/liberty/liberty.cc

@@ -545,12 +545,8 @@ struct LibertyFrontend : public Frontend {
 		std::map<std::string, std::tuple<int, int, bool>> global_type_map;
 		parse_type_map(global_type_map, parser.ast);
 
-		string leakage_power_unit = "";
 		for (auto cell : parser.ast->children)
 		{
-			if (cell->id == "leakage_power_unit")
-				leakage_power_unit = cell->value;
-
 			if (cell->id != "cell" || cell->args.size() != 1)
 				continue;
 
@@ -562,8 +558,6 @@ struct LibertyFrontend : public Frontend {
 			RTLIL::Module *module = new RTLIL::Module;
 			std::string cell_name = RTLIL::escape_id(cell->args.at(0));
 			module->name = cell_name;
-			if (leakage_power_unit != "")
-				module->attributes["\\leakage_power_unit"] = leakage_power_unit;
 
 			if (flag_lib)
 				module->set_bool_attribute(ID::blackbox);
@@ -580,12 +574,6 @@ struct LibertyFrontend : public Frontend {
 
 			for (auto node : cell->children)
 			{
-				if (node->id == "area")
-					module->attributes["\\area"] = node->value;
-
-				if (node->id == "cell_leakage_power")
-					module->attributes["\\LeakagePower"] = node->value;
-
 				if (node->id == "pin" && node->args.size() == 1) {
 					const LibertyAst *dir = node->find("direction");
 					if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
@@ -648,52 +636,6 @@ struct LibertyFrontend : public Frontend {
 					if (dir->value == "output" || dir->value == "inout")
 						wire->port_output = true;
 				}
-
-				if (node->id == "bundle" && node->args.size() == 1)
-				{
-					if (!flag_lib)
-						log_error("Error in cell %s: bundle interfaces are only supported in -lib mode.\n", log_id(cell_name));
-
-					const LibertyAst *dir = node->find("direction");
-
-					if (dir == nullptr) {
-						const LibertyAst *pin = node->find("pin");
-						if (pin != nullptr)
-							dir = pin->find("direction");
-					}
-
-					if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
-						log_error("Missing or invalid direction for bundle %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
-
-					if (dir->value == "internal")
-						continue;
-
-					const LibertyAst *members = node->find("members");
-
-					if (!members)
-						log_error("Missing members for bundle %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
-
-					for (auto member : members->args)
-					{
-						Wire *wire = module->addWire(RTLIL::escape_id(member));
-
-						if (dir && dir->value == "inout") {
-							wire->port_input = true;
-							wire->port_output = true;
-						}
-
-						if (dir && dir->value == "input") {
-							wire->port_input = true;
-							continue;
-						}
-
-						if (dir && dir->value == "output")
-							wire->port_output = true;
-
-						if (flag_lib)
-							continue;
-					}
-				}
 			}
 
 			if (!flag_lib)
@@ -830,4 +772,3 @@ skip_cell:;
 } LibertyFrontend;
 
 YOSYS_NAMESPACE_END
-

tests/liberty/bundledef.lib

@@ -1,62 +0,0 @@
-/* Liberty 2007: example 2-4          */
-/* Direction of pins in bundle groups */
-library(bundle_example) {
-  technology (cmos);
-  revision : 1.0;
-  
-  time_unit                     : "1ps";
-  pulling_resistance_unit       : "1kohm";  
-  voltage_unit                  : "1V";
-  current_unit                  : "1uA";  
-  
-  capacitive_load_unit(1,ff);
-  
-  default_inout_pin_cap         :  7.0;
-  default_input_pin_cap         :  7.0;
-  default_output_pin_cap        :  0.0;
-  default_fanout_load           :  1.0;
-
-  default_wire_load_capacitance : 0.1;
-  default_wire_load_resistance  : 1.0e-3;
-  default_wire_load_area        : 0.0;
-
-  nom_process                   :  1.0;
-  nom_temperature               : 25.0;
-  nom_voltage                   :  1.2;
-  
-  delay_model                   : generic_cmos;
-  
-  cell (inv) {
-    area : 16;
-    cell_leakage_power : 8;
-    bundle (Z) {
-      members (Z0, Z1, Z2, Z3);
-      direction : output;
-      function : "D";
-      pin (Z0) {
-        direction : output;
-        timing () {
-          intrinsic_rise : 0.4;
-          intrinsic_fall : 0.4;
-          related_pin : "D0";
-        }
-      }
-      pin (Z1) {
-        direction : output;
-        timing () {
-          intrinsic_rise : 0.4;
-          intrinsic_fall : 0.4;
-          related_pin : "D1";
-        }
-      }
-    }
-    bundle (D) {
-      members (D0, D1, D2, D3);
-      direction : input;
-      capacitance : 1;
-      pin (D0) {
-        direction : input;
-      }
-    }
-  }
-}

tests/liberty/bundledef.lib.filtered.ok

@@ -1,5 +0,0 @@
-library(bundle_example) {
-  cell(inv) {
-    area : 16 ;
-  }
-}

tests/liberty/bundledef.lib.verilogsim.ok

@@ -1,2 +0,0 @@
-module inv ();
-endmodule

tests/liberty/parenfunc.lib

@@ -1,100 +0,0 @@
-
-library(supergate) {
-  technology (cmos);
-  revision : 1.0;
-  
-  time_unit                     : "1ps";
-  pulling_resistance_unit       : "1kohm";  
-  voltage_unit                  : "1V";
-  current_unit                  : "1uA";  
-  
-  capacitive_load_unit(1,ff);
-  
-  default_inout_pin_cap         :  7.0;
-  default_input_pin_cap         :  7.0;
-  default_output_pin_cap        :  0.0;
-  default_fanout_load           :  1.0;
-
-  default_wire_load_capacitance : 0.1;
-  default_wire_load_resistance  : 1.0e-3;
-  default_wire_load_area        : 0.0;
-
-  input_threshold_pct_rise : 50;
-  input_threshold_pct_fall : 50;
-  output_threshold_pct_rise : 50;
-  output_threshold_pct_fall : 50;
-  slew_lower_threshold_pct_rise : 30;
-  slew_lower_threshold_pct_fall : 30;
-  slew_upper_threshold_pct_rise : 70;
-  slew_upper_threshold_pct_fall : 70;
-
-  nom_process                   :  1.0;
-  nom_temperature               : 25.0;
-  nom_voltage                   :  1.2;
-  
-  delay_model                   : generic_cmos;
-  
-  /* Latch */
-  cell(latch) {
-    area : 5;
-    latch ("IQ","IQN") {
-      enable : (G);
-      data_in : "D";
-    }
-
-    pin(D) {
-      direction : input;
-    }
-    pin(G) {
-      direction : input;
-    }
- 
-    pin(Q) {
-      direction : output;
-      function : "IQ";
-      internal_node : "Q";
-      
-      timing() {
-        timing_type : rising_edge;
-        intrinsic_rise : 65;
-        intrinsic_fall : 65;
-        rise_resistance : 0;
-        fall_resistance : 0;
-        related_pin : "G";
-      }
-      
-      timing() {
-        timing_sense : positive_unate;
-        intrinsic_rise : 65;
-        intrinsic_fall : 65;
-        rise_resistance : 0;
-        fall_resistance : 0;
-        related_pin : "D";
-      }
-    }
-    
-    pin(QN) {
-      direction : output;
-      function : "IQN";
-      internal_node : "QN";
-      
-      timing() {
-        timing_type : rising_edge;
-        intrinsic_rise : 65;
-        intrinsic_fall : 65;
-        rise_resistance : 0;
-        fall_resistance : 0;
-        related_pin : "G";
-      }
-      
-      timing() {
-        timing_sense : negative_unate;
-        intrinsic_rise : 65;
-        intrinsic_fall : 65;
-        rise_resistance : 0;
-        fall_resistance : 0;
-        related_pin : "D";
-      }
-    }
-  }
-}

tests/liberty/parenfunc.lib.filtered.ok

@@ -1,23 +0,0 @@
-library(supergate) {
-  cell(latch) {
-    area : 5 ;
-    latch(IQ, IQN) {
-      enable : (G) ;
-      data_in : D ;
-    }
-    pin(D) {
-      direction : input ;
-    }
-    pin(G) {
-      direction : input ;
-    }
-    pin(Q) {
-      direction : output ;
-      function : IQ ;
-    }
-    pin(QN) {
-      direction : output ;
-      function : IQN ;
-    }
-  }
-}

tests/liberty/parenfunc.lib.verilogsim.ok

@@ -1,15 +0,0 @@
-module latch (D, G, Q, QN);
-  reg IQ, IQN;
-  input D;
-  input G;
-  output Q;
-  assign Q = IQ; // IQ
-  output QN;
-  assign QN = IQN; // IQN
-  always @* begin
-    if ((G)) begin
-      IQ <= D;
-      IQN <= ~(D);
-    end
-  end
-endmodule

tests/liberty/strangecolons.lib

@@ -1,55 +0,0 @@
-library (strange_colons) {
-  delay_model : "table_lookup";
-  simulation : false;
-  capacitive_load_unit (1,pF);
-  leakage_power_unit : "1pW";
-  current_unit : "1A";
-  pulling_resistance_unit : "1kohm";
-  time_unit : "1ns";
-  voltage_unit : "1v";
-  library_features : "report_delay_calculation";
-  input_threshold_pct_rise : 50;
-  input_threshold_pct_fall : 50;
-  output_threshold_pct_rise : 50;
-  output_threshold_pct_fall : 50;
-  slew_lower_threshold_pct_rise : 30;
-  slew_lower_threshold_pct_fall : 30;
-  slew_upper_threshold_pct_rise : 70;
-  slew_upper_threshold_pct_fall : 70;
-  slew_derate_from_library : 1.0;
-  nom_process : 1.0;
-  nom_temperature : 85.0;
-  nom_voltage : 0.75;
-
-  cell(strange_colons) { 
-    sensitization_master : sensitization_3pins ; 
-    area : 0.1 ; 
-    dont_touch : true ; 
-    dont_use : true ; 
-
-    pin(A) { 
-      capacitance : 0.0001 ; 
-      direction : input ; 
-      driver_waveform_rise : "driver_waveform_default_rise" ; 
-      driver_waveform_fall : "driver_waveform_default_fall" ; 
-      fall_capacitance : 0.0001 ; 
-      input_voltage : default ; 
-      max_transition : 0.1 ; 
-      related_ground_pin : VSS ; 
-      related_power_pin : VDD ; 
-      rise_capacitance : 0.0001 ; 
-      active_input_ccb(strange_colons:ck);
-      active_input_ccb(strange_colons:d, \
-                       strange_colons:d);
-      propagating_ccb(strange_colons:a, strange_colons:y);
-
-      input_ccb(strange_colons:a) { 
-        is_needed : true ; 
-        is_inverting : true ; 
-        miller_cap_fall : 0.0001 ; 
-        miller_cap_rise : 1e-05 ; 
-        stage_type : both ; 
-      }
-    }
-  }
-}

tests/liberty/strangecolons.lib.filtered.ok

@@ -1,10 +0,0 @@
-library(strange_colons) {
-  cell(strange_colons) {
-    area : 0.1 ;
-    dont_touch : true ;
-    dont_use : true ;
-    pin(A) {
-      direction : input ;
-    }
-  }
-}

tests/liberty_verilog/.gitignore

@@ -1,3 +0,0 @@
-*.log
-test.ys
-*.lib.v

tests/liberty_verilog/bundledef.lib

@@ -1,62 +0,0 @@
-/* Liberty 2007: example 2-4          */
-/* Direction of pins in bundle groups */
-library(bundle_example) {
-  technology (cmos);
-  revision : 1.0;
-  
-  time_unit                     : "1ps";
-  pulling_resistance_unit       : "1kohm";  
-  voltage_unit                  : "1V";
-  current_unit                  : "1uA";  
-  
-  capacitive_load_unit(1,ff);
-  
-  default_inout_pin_cap         :  7.0;
-  default_input_pin_cap         :  7.0;
-  default_output_pin_cap        :  0.0;
-  default_fanout_load           :  1.0;
-
-  default_wire_load_capacitance : 0.1;
-  default_wire_load_resistance  : 1.0e-3;
-  default_wire_load_area        : 0.0;
-
-  nom_process                   :  1.0;
-  nom_temperature               : 25.0;
-  nom_voltage                   :  1.2;
-  
-  delay_model                   : generic_cmos;
-  
-  cell (inv) {
-    area : 16;
-    cell_leakage_power : 8;
-    bundle (Z) {
-      members (Z0, Z1, Z2, Z3);
-      direction : output;
-      function : "D";
-      pin (Z0) {
-        direction : output;
-        timing () {
-          intrinsic_rise : 0.4;
-          intrinsic_fall : 0.4;
-          related_pin : "D0";
-        }
-      }
-      pin (Z1) {
-        direction : output;
-        timing () {
-          intrinsic_rise : 0.4;
-          intrinsic_fall : 0.4;
-          related_pin : "D1";
-        }
-      }
-    }
-    bundle (D) {
-      members (D0, D1, D2, D3);
-      direction : input;
-      capacitance : 1;
-      pin (D0) {
-        direction : input;
-      }
-    }
-  }
-}

tests/liberty_verilog/bundledef.lib.v.ok

@@ -1,21 +0,0 @@
-(* LeakagePower = "8" *)
-(* area = "16" *)
-(* blackbox =  1  *)
-module inv(Z0, Z1, Z2, Z3, D0, D1, D2, D3);
-  input D0;
-  wire D0;
-  input D1;
-  wire D1;
-  input D2;
-  wire D2;
-  input D3;
-  wire D3;
-  output Z0;
-  wire Z0;
-  output Z1;
-  wire Z1;
-  output Z2;
-  wire Z2;
-  output Z3;
-  wire Z3;
-endmodule

tests/liberty_verilog/busdef.lib

@@ -1,81 +0,0 @@
-/********************************************/
-/*                                          */
-/* Supergate cell library for Bench marking */
-/*                                          */
-/* Symbiotic EDA GmbH / Moseley Instruments */
-/* Niels A. Moseley                         */
-/*                                          */
-/* Process: none                            */
-/*                                          */
-/* Date   : 02-11-2018                      */
-/* Version: 1.0                             */
-/* TODO: FIX THE RESULTS                    */
-/********************************************/
-
-library(supergate) {
-  technology (cmos);
-  revision : 1.0;
-  
-  time_unit                     : "1ps";
-  pulling_resistance_unit       : "1kohm";  
-  voltage_unit                  : "1V";
-  current_unit                  : "1uA";  
-  
-  capacitive_load_unit(1,ff);
-  
-  default_inout_pin_cap         :  7.0;
-  default_input_pin_cap         :  7.0;
-  default_output_pin_cap        :  0.0;
-  default_fanout_load           :  1.0;
-
-  default_wire_load_capacitance : 0.1;
-  default_wire_load_resistance  : 1.0e-3;
-  default_wire_load_area        : 0.0;
-
-  nom_process                   :  1.0;
-  nom_temperature               : 25.0;
-  nom_voltage                   :  1.2;
-  
-  delay_model                   : generic_cmos;
-  
-    type( IO_bus_3_to_0 ) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 4;
-        bit_from : 3 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-
-    cell (SRAM) {
-        area : 1 ;
-        memory() {
-            type : ram;
-            address_width : 4;
-            word_width : 4;
-        }
-        pin(CE1) {
-            direction : input;
-            capacitance : 0.021;
-            max_transition : 1.024;
-            switch_pin : true;
-        }
-        bus(I1)  {
-            bus_type : IO_bus_3_to_0 ;
-            direction : input;
-            pin (I1[3:0]) {
-                timing() {
-                    related_pin :   "CE1" ;
-                    timing_type : setup_rising ;
-                    rise_constraint (scalar) {
-                        values("0.0507786");
-                    }
-                    fall_constraint (scalar) {
-                        values("0.0507786");
-                    }
-                }
-            }
-        }
-    }
-
-} /* end */

tests/liberty_verilog/busdef.lib.v.ok

@@ -1,8 +0,0 @@
-(* area = "1" *)
-(* blackbox =  1  *)
-module SRAM(CE1, I1);
-  input CE1;
-  wire CE1;
-  input [3:0] I1;
-  wire [3:0] I1;
-endmodule

tests/liberty_verilog/busdef2.lib

@@ -1,45 +0,0 @@
-/* Tests two things:                                                      */
-/* (1) Bus without any individual pin definition                          */
-/* (2) Having a custom field with define, which can allow square brackets */
-library (liberty_define) {
-  delay_model : "table_lookup" ;
-  simulation : false ;
-  capacitive_load_unit (1,pF) ;
-  leakage_power_unit : "1pW" ;
-  current_unit : "1A" ;
-  pulling_resistance_unit : "1kohm" ;
-  time_unit : "1ns" ;
-  voltage_unit : "1v" ;
-  library_features : "report_delay_calculation" ;
-  input_threshold_pct_rise : 50 ;
-  input_threshold_pct_fall : 50 ;
-  output_threshold_pct_rise : 50 ;
-  output_threshold_pct_fall : 50 ;
-  slew_lower_threshold_pct_rise : 30 ;
-  slew_lower_threshold_pct_fall : 30 ;
-  slew_upper_threshold_pct_rise : 70 ;
-  slew_upper_threshold_pct_fall : 70 ;
-  slew_derate_from_library : 1.0 ;
-  nom_process : 1.0 ;
-  nom_temperature : 85.0 ;
-  nom_voltage : 0.75 ;
-  type (bus8) {
-    base_type : "array";
-    data_type : "bit";
-    bit_width : 8;
-    bit_from : 7;
-    bit_to : 0;
-  }
-  define (original_pin, pin, string) ;
-  cell (not_cell) {
-    bus (A) {
-      bus_type : "bus8" ;
-      direction : "input" ;
-    }
-    pin (Y) {
-      function : !A[0] ;
-      direction : "output" ;
-      original_pin : A[0] ;
-    }
-  }
-}

tests/liberty_verilog/busdef2.lib.v.ok

@@ -1,8 +0,0 @@
-(* blackbox =  1  *)
-(* leakage_power_unit = "1pW" *)
-module not_cell(A, Y);
-  input [7:0] A;
-  wire [7:0] A;
-  output Y;
-  wire Y;
-endmodule

tests/liberty_verilog/run-test.sh

@@ -1,11 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-for x in *.lib; do
-	echo "Testing on $x.."
-	echo "read_liberty -lib $x" > test.ys
-	echo "write_verilog -blackboxes $x.v.tmp" >> test.ys
-	../../yosys -ql ${x%.lib}.log -s test.ys
-	sed '1,2d' $x.v.tmp > $x.v
-	diff $x.v $x.v.ok
-done