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Assume x values for missing signal data in FST

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Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
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Roland Coeurjoly 2024-10-02 11:18:19 +02:00
parent 1bf908dea8
commit 5ea2c6e6e5
4 changed files with 26 additions and 2 deletions
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13
tests/sim/simple_assign.vcd Normal file
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@ -0,0 +1,13 @@
$version Yosys $end
$scope module simple_assign $end
$var wire 1 n2 in $end
$var wire 1 n1 out $end
$upscope $end
$enddefinitions $end
#0
#5
b1 n1
b1 n2
#10
b0 n1
b0 n2