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	Assume x values for missing signal data in FST
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
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					 4 changed files with 26 additions and 2 deletions
				
			
		
							
								
								
									
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								tests/sim/simple_assign.v
									
										
									
									
									
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								tests/sim/simple_assign.v
									
										
									
									
									
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							|  | @ -0,0 +1,8 @@ | |||
| module simple_assign ( | ||||
|     input wire in, | ||||
|     output wire out | ||||
| ); | ||||
| 
 | ||||
|     assign out = in; | ||||
| 
 | ||||
| endmodule | ||||
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