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Assume x values for missing signal data in FST

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Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
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Roland Coeurjoly 2024-10-02 11:18:19 +02:00
parent 1bf908dea8
commit 5ea2c6e6e5
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tests/sim/assume_x_first_step.ys Normal file
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read_verilog simple_assign.v
sim -r simple_assign.vcd -scope simple_assign