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hierarchy: Resolve SV wildcard port connections

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-11-22 09:04:54 +00:00
parent 50f86c11b2
commit 5df591c023
2 changed files with 63 additions and 4 deletions
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2
frontends/verilog/verilog_parser.y
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@ -1582,7 +1582,7 @@ cell_port:
free_attr($1);
} |
attr TOK_AUTOCONNECT_ALL {
astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false);
astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false);
};
always_comb_or_latch: