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signorm: add timers

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This commit is contained in:
Emil J. Tywoniak 2026-05-06 12:14:48 +02:00
parent 5de8452b57
commit 5dce475325
3 changed files with 25 additions and 0 deletions
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4
kernel/driver.cc
View file

@ -713,6 +713,10 @@ int main(int argc, char **argv)
total_ns += gc_ns; total_ns += gc_ns;
timedat.insert(make_tuple(gc_ns, timedat.insert(make_tuple(gc_ns,
RTLIL::OwningIdString::garbage_collection_count(), "id_gc")); RTLIL::OwningIdString::garbage_collection_count(), "id_gc"));
total_ns += signorm_ns;
timedat.insert(make_tuple(signorm_ns, signorm_count, "signorm"));
total_ns += signorm_restore_ns;
timedat.insert(make_tuple(signorm_restore_ns, signorm_restore_count, "signorm_restore"));
} }
if (timing_details) if (timing_details)

6
kernel/rtlil.h
View file

@ -129,6 +129,12 @@ namespace RTLIL
struct PortBit; struct PortBit;
}; };
// TODO clean up?
extern int64_t signorm_ns;
extern int signorm_count;
extern int64_t signorm_restore_ns;
extern int signorm_restore_count;
struct RTLIL::IdString struct RTLIL::IdString
{ {
struct Storage { struct Storage {

15
kernel/rtlil_bufnorm.cc
View file

@ -233,6 +233,7 @@ struct RTLIL::SigNormIndex
} }
void restore_connections() { void restore_connections() {
int64_t start = PerformanceTimer::query();
flush_connections(); flush_connections();
pool<Wire *> wires; pool<Wire *> wires;
for (auto const &bit : sigmap.database) for (auto const &bit : sigmap.database)
@ -260,6 +261,11 @@ struct RTLIL::SigNormIndex
} }
restored_connections = module->connections_.size(); restored_connections = module->connections_.size();
int64_t time_ns = PerformanceTimer::query() - start;
Pass::subtract_from_current_runtime_ns(time_ns);
signorm_restore_ns += time_ns;
++signorm_restore_count;
} }
}; };
@ -316,6 +322,10 @@ void RTLIL::Design::bufNormalize(bool enable)
module->bufNormalize(); module->bufNormalize();
} }
int64_t signorm_ns;
int signorm_count;
int64_t signorm_restore_ns;
int signorm_restore_count;
void RTLIL::Design::sigNormalize(bool enable) void RTLIL::Design::sigNormalize(bool enable)
{ {
if (!enable) if (!enable)
@ -357,8 +367,13 @@ void RTLIL::Design::sigNormalize(bool enable)
flagSigNormalized = true; flagSigNormalized = true;
} }
int64_t start = PerformanceTimer::query();
for (auto module : modules()) for (auto module : modules())
module->sigNormalize(); module->sigNormalize();
int64_t time_ns = PerformanceTimer::query() - start;
Pass::subtract_from_current_runtime_ns(time_ns);
signorm_ns += time_ns;
++signorm_count;
} }
void RTLIL::Module::sigNormalize() void RTLIL::Module::sigNormalize()