mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
Changed backend-api from FILE to std::ostream
This commit is contained in:
Clifford Wolf
parent
fff12c719f
commit
5dce303a2a
16 changed files with 710 additions and 725 deletions
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@ -747,11 +747,12 @@ struct ExtractPass : public Pass {
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}
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}
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FILE *f = fopen(mine_outfile.c_str(), "wt");
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if (f == NULL)
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std::ofstream f;
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f.open(mine_outfile.c_str(), std::ofstream::trunc);
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if (f.fail())
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log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
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Backend::backend_call(map, f, mine_outfile, "ilang");
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fclose(f);
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Backend::backend_call(map, &f, mine_outfile, "ilang");
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f.close();
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}
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delete map;
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@ -70,26 +70,26 @@ static std::string idy(std::string str1, std::string str2 = std::string(), std::
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return id(str1);
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}
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static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
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{
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fprintf(f, "module testbench;\n\n");
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f << stringf("module testbench;\n\n");
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fprintf(f, "integer i;\n\n");
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f << stringf("integer i;\n\n");
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fprintf(f, "reg [31:0] xorshift128_x = 123456789;\n");
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fprintf(f, "reg [31:0] xorshift128_y = 362436069;\n");
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fprintf(f, "reg [31:0] xorshift128_z = 521288629;\n");
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fprintf(f, "reg [31:0] xorshift128_w = %u; // <-- seed value\n", int(time(NULL)));
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fprintf(f, "reg [31:0] xorshift128_t;\n\n");
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fprintf(f, "task xorshift128;\n");
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fprintf(f, "begin\n");
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fprintf(f, "\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n");
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fprintf(f, "\txorshift128_x = xorshift128_y;\n");
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fprintf(f, "\txorshift128_y = xorshift128_z;\n");
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fprintf(f, "\txorshift128_z = xorshift128_w;\n");
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fprintf(f, "\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n");
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf("reg [31:0] xorshift128_x = 123456789;\n");
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f << stringf("reg [31:0] xorshift128_y = 362436069;\n");
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f << stringf("reg [31:0] xorshift128_z = 521288629;\n");
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f << stringf("reg [31:0] xorshift128_w = %u; // <-- seed value\n", int(time(NULL)));
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f << stringf("reg [31:0] xorshift128_t;\n\n");
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f << stringf("task xorshift128;\n");
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f << stringf("begin\n");
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f << stringf("\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n");
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f << stringf("\txorshift128_x = xorshift128_y;\n");
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f << stringf("\txorshift128_y = xorshift128_z;\n");
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f << stringf("\txorshift128_z = xorshift128_w;\n");
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f << stringf("\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
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{
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@ -110,7 +110,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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if (wire->port_output) {
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count_ports++;
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signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
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fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
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f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
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} else if (wire->port_input) {
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count_ports++;
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bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
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@ -130,85 +130,85 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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if (wire->attributes.count("\\gentb_constant") != 0)
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signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string();
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}
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fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
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f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
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}
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}
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fprintf(f, "%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
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f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
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for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
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RTLIL::Wire *wire = it2->second;
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if (wire->port_output || wire->port_input)
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fprintf(f, "\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
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f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
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idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
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}
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fprintf(f, ");\n\n");
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f << stringf(");\n\n");
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fprintf(f, "task %s;\n", idy(mod->name.str(), "reset").c_str());
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fprintf(f, "begin\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str());
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f << stringf("begin\n");
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int delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); it++)
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fprintf(f, "\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
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f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
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fprintf(f, "\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
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f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
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fprintf(f, "\t#100; %s <= 1;\n", it->first.c_str());
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fprintf(f, "\t#100; %s <= 0;\n", it->first.c_str());
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f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
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f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
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}
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delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); it++)
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fprintf(f, "\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2);
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f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2);
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
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fprintf(f, "\t#100; %s <= 1;\n", it->first.c_str());
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fprintf(f, "\t#100; %s <= 0;\n", it->first.c_str());
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f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
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f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
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}
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delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
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if (signal_const.count(it->first) == 0)
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continue;
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fprintf(f, "\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str());
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f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str());
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}
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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fprintf(f, "task %s;\n", idy(mod->name.str(), "update_data").c_str());
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fprintf(f, "begin\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str());
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f << stringf("begin\n");
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delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
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if (signal_const.count(it->first) > 0)
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continue;
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fprintf(f, "\txorshift128;\n");
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fprintf(f, "\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2);
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f << stringf("\txorshift128;\n");
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f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2);
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}
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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fprintf(f, "task %s;\n", idy(mod->name.str(), "update_clock").c_str());
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fprintf(f, "begin\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str());
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f << stringf("begin\n");
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if (signal_clk.size()) {
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fprintf(f, "\txorshift128;\n");
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fprintf(f, "\t{");
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f << stringf("\txorshift128;\n");
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f << stringf("\t{");
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int total_clock_bits = 0;
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
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fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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total_clock_bits += it->second;
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}
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fprintf(f, " } = {");
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f << stringf(" } = {");
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
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fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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fprintf(f, " } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits);
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f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits);
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}
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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char shorthand = 'A';
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std::vector<std::string> header1;
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std::string header2 = "";
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fprintf(f, "task %s;\n", idy(mod->name.str(), "print_status").c_str());
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fprintf(f, "begin\n");
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fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {");
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f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str());
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f << stringf("begin\n");
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f << stringf("\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {");
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if (signal_in.size())
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for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
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fprintf(f, "%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
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f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
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int len = it->second;
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if (len > 1)
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header2 += "/", len--;
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@ -220,14 +220,14 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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header1.back()[0] = shorthand++;
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}
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else {
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fprintf(f, " 1'bx");
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f << stringf(" 1'bx");
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header2 += "#";
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}
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fprintf(f, " }, {");
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f << stringf(" }, {");
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header2 += " ";
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if (signal_clk.size()) {
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
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fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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int len = it->second;
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if (len > 1)
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header2 += "/", len--;
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@ -239,14 +239,14 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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header1.back()[0] = shorthand++;
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}
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} else {
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fprintf(f, " 1'bx");
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f << stringf(" 1'bx");
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header2 += "#";
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}
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fprintf(f, " }, {");
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f << stringf(" }, {");
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header2 += " ";
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if (signal_out.size()) {
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for (auto it = signal_out.begin(); it != signal_out.end(); it++) {
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fprintf(f, "%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str());
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f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str());
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int len = it->second;
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if (len > 1)
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header2 += "/", len--;
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@ -258,47 +258,47 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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header1.back()[0] = shorthand++;
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}
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} else {
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fprintf(f, " 1'bx");
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f << stringf(" 1'bx");
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header2 += "#";
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}
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fprintf(f, " }, $time, i);\n");
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf(" }, $time, i);\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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fprintf(f, "task %s;\n", idy(mod->name.str(), "print_header").c_str());
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fprintf(f, "begin\n");
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fprintf(f, "\t$display(\"#OUT#\");\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str());
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f << stringf("begin\n");
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f << stringf("\t$display(\"#OUT#\");\n");
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for (auto &hdr : header1)
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fprintf(f, "\t$display(\"#OUT# %s\");\n", hdr.c_str());
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fprintf(f, "\t$display(\"#OUT#\");\n");
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fprintf(f, "\t$display(\"#OUT# %s\");\n", header2.c_str());
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf("\t$display(\"#OUT# %s\");\n", hdr.c_str());
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f << stringf("\t$display(\"#OUT#\");\n");
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f << stringf("\t$display(\"#OUT# %s\");\n", header2.c_str());
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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fprintf(f, "task %s;\n", idy(mod->name.str(), "test").c_str());
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fprintf(f, "begin\n");
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fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
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fprintf(f, "\t%s;\n", idy(mod->name.str(), "reset").c_str());
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fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
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fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
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fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
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fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
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fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
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fprintf(f, "\tend\n");
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fprintf(f, "end\n");
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fprintf(f, "endtask\n\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str());
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f << stringf("begin\n");
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f << stringf("\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
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f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str());
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f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
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f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
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f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
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f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
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f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
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f << stringf("\tend\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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}
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fprintf(f, "initial begin\n");
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fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
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fprintf(f, "\t// $dumpvars(0, testbench);\n");
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f << stringf("initial begin\n");
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f << stringf("\t// $dumpfile(\"testbench.vcd\");\n");
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f << stringf("\t// $dumpvars(0, testbench);\n");
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for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
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if (!it->second->get_bool_attribute("\\gentb_skip"))
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fprintf(f, "\t%s;\n", idy(it->first.str(), "test").c_str());
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fprintf(f, "\t$finish;\n");
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fprintf(f, "end\n\n");
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f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str());
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f << stringf("\t$finish;\n");
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f << stringf("end\n\n");
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fprintf(f, "endmodule\n");
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f << stringf("endmodule\n");
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}
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struct TestAutotbBackend : public Backend {
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@ -328,7 +328,7 @@ struct TestAutotbBackend : public Backend {
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log(" number of iterations the test bench shuld run (default = 1000)\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
int num_iter = 1000;
|
||||
|
||||
|
|
@ -345,7 +345,7 @@ struct TestAutotbBackend : public Backend {
|
|||
}
|
||||
|
||||
extra_args(f, filename, args, argidx);
|
||||
autotest(f, design, num_iter);
|
||||
autotest(*f, design, num_iter);
|
||||
}
|
||||
} TestAutotbBackend;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue