3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00

Changed backend-api from FILE to std::ostream

This commit is contained in:
Clifford Wolf 2014-08-23 13:54:21 +02:00
parent fff12c719f
commit 5dce303a2a
16 changed files with 710 additions and 725 deletions

View file

@ -24,24 +24,24 @@
#include "kernel/log.h"
#include <string>
static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
{
if (s.wire) {
if (s.wire->width > 1)
fprintf(f, " %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset);
f << stringf(" %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset);
else
fprintf(f, " %s", RTLIL::id2cstr(s.wire->name));
f << stringf(" %s", RTLIL::id2cstr(s.wire->name));
} else {
if (s == RTLIL::State::S0)
fprintf(f, " %s", neg.c_str());
f << stringf(" %s", neg.c_str());
else if (s == RTLIL::State::S1)
fprintf(f, " %s", pos.c_str());
f << stringf(" %s", pos.c_str());
else
fprintf(f, " %s%d", ncpf.c_str(), nc_counter++);
f << stringf(" %s%d", ncpf.c_str(), nc_counter++);
}
}
static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian)
static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian)
{
SigMap sigmap(module);
int cell_counter = 0, conn_counter = 0, nc_counter = 0;
@ -49,7 +49,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
fprintf(f, "X%d", cell_counter++);
f << stringf("X%d", cell_counter++);
std::vector<RTLIL::SigSpec> port_sigs;
@ -94,15 +94,15 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
}
}
fprintf(f, " %s\n", RTLIL::id2cstr(cell->type));
f << stringf(" %s\n", RTLIL::id2cstr(cell->type));
}
for (auto &conn : module->connections())
for (int i = 0; i < conn.first.size(); i++) {
fprintf(f, "V%d", conn_counter++);
f << stringf("V%d", conn_counter++);
print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter);
fprintf(f, " DC 0\n");
f << stringf(" DC 0\n");
}
}
@ -133,7 +133,7 @@ struct SpiceBackend : public Backend {
log(" set the specified module as design top module\n");
log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
std::string top_module_name;
RTLIL::Module *top_module = NULL;
@ -174,8 +174,8 @@ struct SpiceBackend : public Backend {
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first.str();
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n");
*f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
*f << stringf("\n");
for (auto module_it : design->modules_)
{
@ -203,31 +203,31 @@ struct SpiceBackend : public Backend {
ports.at(wire->port_id-1) = wire;
}
fprintf(f, ".SUBCKT %s", RTLIL::id2cstr(module->name));
*f << stringf(".SUBCKT %s", RTLIL::id2cstr(module->name));
for (RTLIL::Wire *wire : ports) {
log_assert(wire != NULL);
if (wire->width > 1) {
for (int i = 0; i < wire->width; i++)
fprintf(f, " %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i);
*f << stringf(" %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i);
} else
fprintf(f, " %s", RTLIL::id2cstr(wire->name));
*f << stringf(" %s", RTLIL::id2cstr(wire->name));
}
fprintf(f, "\n");
print_spice_module(f, module, design, neg, pos, ncpf, big_endian);
fprintf(f, ".ENDS %s\n\n", RTLIL::id2cstr(module->name));
*f << stringf("\n");
print_spice_module(*f, module, design, neg, pos, ncpf, big_endian);
*f << stringf(".ENDS %s\n\n", RTLIL::id2cstr(module->name));
}
if (!top_module_name.empty()) {
if (top_module == NULL)
log_error("Can't find top module `%s'!\n", top_module_name.c_str());
print_spice_module(f, top_module, design, neg, pos, ncpf, big_endian);
fprintf(f, "\n");
print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian);
*f << stringf("\n");
}
fprintf(f, "************************\n");
fprintf(f, "* end of SPICE netlist *\n");
fprintf(f, "************************\n");
fprintf(f, "\n");
*f << stringf("************************\n");
*f << stringf("* end of SPICE netlist *\n");
*f << stringf("************************\n");
*f << stringf("\n");
}
} SpiceBackend;