mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
Changed backend-api from FILE to std::ostream
This commit is contained in:
Clifford Wolf
parent
fff12c719f
commit
5dce303a2a
16 changed files with 710 additions and 725 deletions
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@ -60,7 +60,7 @@ struct WireInfoOrder
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struct BtorDumper
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{
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FILE *f;
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std::ostream &f;
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RTLIL::Module *module;
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RTLIL::Design *design;
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BtorDumperConfig *config;
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@ -75,7 +75,7 @@ struct BtorDumper
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std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers
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RTLIL::IdString curr_cell; //current cell being dumped
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std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
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BtorDumper(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design), sigmap(module)
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{
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line_num=0;
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@ -174,7 +174,7 @@ struct BtorDumper
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++line_num;
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line_ref[wire->name]=line_num;
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str = stringf("%d var %d %s", line_num, wire->width, cstr(wire->name));
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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return line_num;
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}
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else return it->second;
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@ -216,13 +216,13 @@ struct BtorDumper
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wire_line = ++line_num;
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str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks().at(j).width,
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cell_line, start_bit-1, start_bit-cell_output->chunks().at(j).width);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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wire_width += cell_output->chunks().at(j).width;
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if(prev_wire_line!=0)
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{
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++line_num;
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str = stringf("%d concat %d %d %d", line_num, wire_width, wire_line, prev_wire_line);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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wire_line = line_num;
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}
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}
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@ -259,7 +259,7 @@ struct BtorDumper
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int address_bits = ceil(log(memory->size)/log(2));
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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line_ref[memory->name]=line_num;
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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return line_num;
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}
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else return it->second;
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@ -279,7 +279,7 @@ struct BtorDumper
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++line_num;
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str = stringf("%d const %d %s", line_num, width, data_str.c_str());
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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return line_num;
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}
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else
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@ -307,7 +307,7 @@ struct BtorDumper
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++line_num;
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str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num,
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chunk->width + chunk->offset - 1, chunk->offset);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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l = line_num;
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}
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}
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@ -339,7 +339,7 @@ struct BtorDumper
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w2 = s.chunks().at(i).width;
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++line_num;
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str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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l1=line_num;
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w1+=w2;
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}
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@ -361,17 +361,17 @@ struct BtorDumper
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//TODO: case the signal is signed
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++line_num;
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str = stringf ("%d zero %d", line_num, expected_width - s.size());
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf ("%d concat %d %d %d", line_num, expected_width, line_num-1, l);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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l = line_num;
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}
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else if(expected_width < s.size())
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{
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++line_num;
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str = stringf ("%d slice %d %d %d %d;3", line_num, expected_width, l, expected_width-1, 0);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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l = line_num;
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}
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}
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@ -397,21 +397,21 @@ struct BtorDumper
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int en_line = dump_sigspec(en, 1);
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int one_line = ++line_num;
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str = stringf("%d one 1", line_num);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at("$eq").c_str(), 1, en_line, one_line);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 1, line_num-1,
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expr_line, one_line);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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int cell_line = ++line_num;
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str = stringf("%d %s %d %d", line_num, cell_type_translation.at("$assert").c_str(), 1, -1*(line_num-1));
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//multiplying the line number with -1, which means logical negation
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//the reason for negative sign is that the properties in btor are given as "negation of the original property"
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//bug identified by bobosoft
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//http://www.reddit.com/r/yosys/comments/1w3xig/btor_backend_bug/
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=cell_line;
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}
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//unary cells
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@ -429,13 +429,13 @@ struct BtorDumper
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cell_line = ++line_num;
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bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
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str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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if(output_width < w && (cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos"))
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{
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++line_num;
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str = stringf ("%d slice %d %d %d %d;4", line_num, output_width, cell_line, output_width-1, 0);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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cell_line = line_num;
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}
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line_ref[cell->name]=cell_line;
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@ -451,17 +451,17 @@ struct BtorDumper
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{
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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else if(cell->type == "$reduce_xnor")
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{
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_xor").c_str(), output_width, l);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$not").c_str(), output_width, line_num-1);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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//binary cells
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@ -497,7 +497,7 @@ struct BtorDumper
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}
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str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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@ -532,13 +532,13 @@ struct BtorDumper
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op = s_cell_type_translation.at("$mody");
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}
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str = stringf ("%d %s %d %d %d", line_num, op.c_str(), l1_width, l1, l2);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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if(output_width < l1_width)
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{
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++line_num;
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str = stringf ("%d slice %d %d %d %d;5", line_num, output_width, line_num-1, output_width-1, 0);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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line_ref[cell->name]=line_num;
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}
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@ -556,7 +556,7 @@ struct BtorDumper
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int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
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int cell_output = ++line_num;
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str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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if(l2_width > ceil(log(l1_width)/log(2)))
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{
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@ -564,19 +564,19 @@ struct BtorDumper
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l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
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++line_num;
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str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf ("%d one %d", line_num, extra_width);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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int mux = ++line_num;
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str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at("$gt").c_str(), 1, line_num-2, line_num-1);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d %s %d", line_num, l1_signed && cell->type == "$sshr" ? "ones":"zero", l1_width);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf ("%d %s %d %d %d %d", line_num, cell_type_translation.at("$mux").c_str(), l1_width, mux, line_num-1, cell_output);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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cell_output = line_num;
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}
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@ -584,7 +584,7 @@ struct BtorDumper
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{
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++line_num;
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str = stringf ("%d slice %d %d %d %d;5", line_num, output_width, cell_output, output_width-1, 0);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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cell_output = line_num;
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}
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line_ref[cell->name] = cell_output;
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@ -602,14 +602,14 @@ struct BtorDumper
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{
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l1);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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l1 = line_num;
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}
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if(l2_width > 1)
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{
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l2);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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l2 = line_num;
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}
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if(cell->type == "$logic_and")
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@ -622,7 +622,7 @@ struct BtorDumper
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++line_num;
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str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at("$or").c_str(), output_width, l1, l2);
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}
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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//multiplexers
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@ -636,7 +636,7 @@ struct BtorDumper
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++line_num;
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str = stringf ("%d %s %d %d %d %d",
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line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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//registers
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@ -663,7 +663,7 @@ struct BtorDumper
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slice = ++line_num;
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str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1,
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start_bit-output_width);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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if(cell->type == "$dffsr")
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{
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@ -676,14 +676,14 @@ struct BtorDumper
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str = stringf ("%d %s %d %s%d %s%d %d", line_num, cell_type_translation.at("$mux").c_str(),
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output_width, sync_reset_pol ? "":"-", sync_reset, sync_reset_value_pol? "":"-",
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sync_reset_value, slice);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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slice = line_num;
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}
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++line_num;
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str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(),
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output_width, polarity?"":"-", cond, slice, reg);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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int next = line_num;
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if(cell->type == "$adff")
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{
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@ -694,12 +694,12 @@ struct BtorDumper
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++line_num;
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str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(),
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output_width, async_reset_pol ? "":"-", async_reset, async_reset_value, next);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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++line_num;
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str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(),
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output_width, reg, next);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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}
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line_ref[cell->name]=line_num;
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}
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@ -716,7 +716,7 @@ struct BtorDumper
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int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
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++line_num;
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str = stringf("%d read %d %d %d", line_num, data_width, mem, address);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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else if(cell->type == "$memwr")
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@ -738,22 +738,22 @@ struct BtorDumper
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str = stringf("%d one 1", line_num);
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else
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str = stringf("%d zero 1", line_num);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d eq 1 %d %d", line_num, clk, line_num-1);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d and 1 %d %d", line_num, line_num-1, enable);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2/*enable*/, line_num-1, mem);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);
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fprintf(f, "%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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else if(cell->type == "$slice")
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@ -769,7 +769,7 @@ struct BtorDumper
|
|||
int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
|
||||
++line_num;
|
||||
str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
|
||||
fprintf(f, "%s\n", str.c_str());
|
||||
f << stringf("%s\n", str.c_str());
|
||||
line_ref[cell->name]=line_num;
|
||||
}
|
||||
else if(cell->type == "$concat")
|
||||
|
|
@ -786,7 +786,7 @@ struct BtorDumper
|
|||
++line_num;
|
||||
str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width,
|
||||
input_a_line, input_b_line);
|
||||
fprintf(f, "%s\n", str.c_str());
|
||||
f << stringf("%s\n", str.c_str());
|
||||
line_ref[cell->name]=line_num;
|
||||
}
|
||||
curr_cell.clear();
|
||||
|
|
@ -825,12 +825,12 @@ struct BtorDumper
|
|||
int l = dump_wire(wire);
|
||||
++line_num;
|
||||
str = stringf("%d root 1 %d", line_num, l);
|
||||
fprintf(f, "%s\n", str.c_str());
|
||||
f << stringf("%s\n", str.c_str());
|
||||
}
|
||||
|
||||
void dump()
|
||||
{
|
||||
fprintf(f, ";module %s\n", cstr(module->name));
|
||||
f << stringf(";module %s\n", cstr(module->name));
|
||||
|
||||
log("creating intermediate wires map\n");
|
||||
//creating map of intermediate wires as output of some cell
|
||||
|
|
@ -893,12 +893,12 @@ struct BtorDumper
|
|||
}
|
||||
}
|
||||
|
||||
fprintf(f, ";inputs\n");
|
||||
f << stringf(";inputs\n");
|
||||
for (auto &it : inputs) {
|
||||
RTLIL::Wire *wire = it.second;
|
||||
dump_wire(wire);
|
||||
}
|
||||
fprintf(f, "\n");
|
||||
f << stringf("\n");
|
||||
|
||||
log("writing memories\n");
|
||||
for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it)
|
||||
|
|
@ -921,19 +921,19 @@ struct BtorDumper
|
|||
for(auto it: safety)
|
||||
dump_property(it);
|
||||
|
||||
fprintf(f, "\n");
|
||||
f << stringf("\n");
|
||||
|
||||
log("writing outputs info\n");
|
||||
fprintf(f, ";outputs\n");
|
||||
f << stringf(";outputs\n");
|
||||
for (auto &it : outputs) {
|
||||
RTLIL::Wire *wire = it.second;
|
||||
int l = dump_wire(wire);
|
||||
fprintf(f, ";%d %s", l, cstr(wire->name));
|
||||
f << stringf(";%d %s", l, cstr(wire->name));
|
||||
}
|
||||
fprintf(f, "\n");
|
||||
f << stringf("\n");
|
||||
}
|
||||
|
||||
static void dump(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig &config)
|
||||
static void dump(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig &config)
|
||||
{
|
||||
BtorDumper dumper(f, module, design, &config);
|
||||
dumper.dump();
|
||||
|
|
@ -952,7 +952,7 @@ struct BtorBackend : public Backend {
|
|||
log("Write the current design to an BTOR file.\n");
|
||||
}
|
||||
|
||||
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
|
||||
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
std::string top_module_name;
|
||||
std::string buf_type, buf_in, buf_out;
|
||||
|
|
@ -970,10 +970,10 @@ struct BtorBackend : public Backend {
|
|||
if (mod_it.second->get_bool_attribute("\\top"))
|
||||
top_module_name = mod_it.first.str();
|
||||
|
||||
fprintf(f, "; Generated by %s\n", yosys_version_str);
|
||||
fprintf(f, "; %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
|
||||
fprintf(f, "; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n");
|
||||
fprintf(f, ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n");
|
||||
*f << stringf("; Generated by %s\n", yosys_version_str);
|
||||
*f << stringf("; %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
|
||||
*f << stringf("; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n");
|
||||
*f << stringf(";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n");
|
||||
|
||||
std::vector<RTLIL::Module*> mod_list;
|
||||
|
||||
|
|
@ -987,7 +987,7 @@ struct BtorBackend : public Backend {
|
|||
log_error("Found unmapped processes in module %s: unmapped processes are not supported in BTOR backend!\n", RTLIL::id2cstr(module->name));
|
||||
|
||||
if (module->name == RTLIL::escape_id(top_module_name)) {
|
||||
BtorDumper::dump(f, module, design, config);
|
||||
BtorDumper::dump(*f, module, design, config);
|
||||
top_module_name.clear();
|
||||
continue;
|
||||
}
|
||||
|
|
@ -999,7 +999,7 @@ struct BtorBackend : public Backend {
|
|||
log_error("Can't find top module `%s'!\n", top_module_name.c_str());
|
||||
|
||||
for (auto module : mod_list)
|
||||
BtorDumper::dump(f, module, design, config);
|
||||
BtorDumper::dump(*f, module, design, config);
|
||||
}
|
||||
} BtorBackend;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue