mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 03:57:52 +00:00
Code Activity

intel_alm: Add IO buffer insertion

Browse source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-15 14:23:22 +01:00
parent 3421979f00
commit 5dba138c87
19 changed files with 166 additions and 46 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/arch/intel_alm/tribuf.ys
View file

@ -4,7 +4,7 @@ proc
tribuf
flatten
synth
equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev # equivalency check
equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.
@ -19,7 +19,7 @@ proc
tribuf
flatten
synth
equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx # equivalency check
equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.