mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

intel_alm: Add IO buffer insertion

Browse source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-15 14:23:22 +01:00
parent 3421979f00
commit 5dba138c87
19 changed files with 166 additions and 46 deletions
Download patch file Download diff file Expand all files Collapse all files

28
techlibs/intel_alm/cyclonev/cells_sim.v
View file

@ -26,16 +26,34 @@ endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */
module cyclonev_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
(output o,
(* iopad_external_pin *) input i,
(* iopad_external_pin *) input ibar,
input dynamicterminationcontrol);
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cyclonev_io_ibuf";
assign o = i;
endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */
module cyclonev_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
((* iopad_external_pin *) output o,
input i, oe, dynamicterminationcontrol,
input [15:0] seriesterminationcontrol, parallelterminationcontrol,
input devoe,
(* iopad_external_pin *) output obar);
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
parameter sim_dynamic_termination_control_is_connected = "false";
parameter lpm_type = "cyclonev_io_obuf";
assign o = oe ? i : 1'bz;
endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */