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More fixes in ast expression sign/width handling

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This commit is contained in:
Clifford Wolf 2013-07-09 23:41:28 +02:00
parent 618b2ac994
commit 5dab327b30
2 changed files with 22 additions and 21 deletions
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26
tests/simple/vloghammer.v
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@ -27,19 +27,21 @@ module test04(a, y);
assign y = ~(a - 1'b0);
endmodule
module test05(a, y);
input a;
output y;
assign y = 12345 >> {a, 32'd0};
endmodule
// .. this test triggers a bug in xilinx isim.
// module test05(a, y);
// input a;
// output y;
// assign y = 12345 >> {a, 32'd0};
// endmodule
module test06(a, b, c, y);
input signed [3:0] a;
input signed [1:0] b;
input signed [1:0] c;
output [5:0] y;
assign y = (a >> b) >>> c;
endmodule
// .. this test triggers a bug in icarus verilog.
// module test06(a, b, c, y);
// input signed [3:0] a;
// input signed [1:0] b;
// input signed [1:0] c;
// output [5:0] y;
// assign y = (a >> b) >>> c;
// endmodule
module test07(a, b, y);
input signed [1:0] a;