mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-17 16:52:16 +00:00
Code Activity

Add "verific -L <int>" option

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-09-04 20:06:10 +02:00
parent 0b7a18470b
commit 5d9d22f66d
3 changed files with 16 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

5
frontends/verific/verificsva.cc
View file

@ -466,13 +466,14 @@ struct SvaFsm
dnode.ctrl.sort_and_unify();
if (GetSize(dnode.ctrl) > 16) {
if (GetSize(dnode.ctrl) > verific_sva_fsm_limit) {
if (verific_verbose >= 2) {
log(" detected state explosion in DFSM generation:\n");
dump();
log(" ctrl signal: %s\n", log_signal(dnode.ctrl));
}
log_error("SVA DFSM state ctrl signal has %d (>16) bits. Stopping to prevent exponential design size explosion.\n", GetSize(dnode.ctrl));
log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n",
GetSize(dnode.ctrl), verific_sva_fsm_limit);
}
for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++)