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Use equiv_opt -async2sync for xilinx

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This commit is contained in:
Eddie Hung 2019-10-03 10:30:33 -07:00
parent 8765ec3c27
commit 5d680590d6
1 changed files with 1 additions and 3 deletions
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4
tests/xilinx/latches.ys
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@ -2,9 +2,7 @@ read_verilog latches.v
proc proc
flatten flatten
equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
async2sync
equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load preopt design -load preopt
synth_xilinx synth_xilinx