mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-02 07:07:56 +00:00
analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests. Remove BUFG from `lutram.ys`. Extra `sync_ram_sp` models in `arch/common/blockram.v`. Add analogdevices to main makefile tests. Not all the other tests are passing, but that's fine for now.
This commit is contained in:
parent
f06018306d
commit
5d3ed5a418
6 changed files with 211 additions and 13 deletions
1
tests/arch/analogdevices/.gitignore
vendored
Normal file
1
tests/arch/analogdevices/.gitignore
vendored
Normal file
|
|
@ -0,0 +1 @@
|
|||
t_*.ys
|
||||
Loading…
Add table
Add a link
Reference in a new issue