mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

flatten: simplify. NFC.

Browse source 
Flatten is non-recursive and doesn't need to keep track of handled
cells.
This commit is contained in:
whitequark 2020-06-03 02:28:39 +00:00
parent 3c3fa774e5
commit 5d2b6d1394
1 changed files with 4 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
passes/techmap/flatten.cc
View file

@ -249,7 +249,7 @@ struct FlattenWorker
} }
} }
bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Cell*> &handled_cells) bool flatten_module(RTLIL::Design *design, RTLIL::Module *module)
{ {
if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
return false; return false;
@ -266,9 +266,6 @@ struct FlattenWorker
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (handled_cells.count(cell) > 0)
continue;
if (!design->has(cell->type)) if (!design->has(cell->type))
continue; continue;
@ -311,16 +308,13 @@ struct FlattenWorker
for (auto cell : cells.sorted) for (auto cell : cells.sorted)
{ {
log_assert(handled_cells.count(cell) == 0);
log_assert(cell == module->cell(cell->name)); log_assert(cell == module->cell(cell->name));
RTLIL::Module *tpl = design->module(cell->type); RTLIL::Module *tpl = design->module(cell->type);
dict<IdString, RTLIL::Const> parameters(cell->parameters); dict<IdString, RTLIL::Const> parameters(cell->parameters);
if (tpl->get_blackbox_attribute(ignore_wb)) { if (tpl->get_blackbox_attribute(ignore_wb))
handled_cells.insert(cell);
continue; continue;
}
std::pair<IdString, dict<IdString, RTLIL::Const>> key(cell->type, parameters); std::pair<IdString, dict<IdString, RTLIL::Const>> key(cell->type, parameters);
IdString derived_name; IdString derived_name;
@ -401,18 +395,17 @@ struct FlattenPass : public Pass {
if (mod->get_bool_attribute(ID::top)) if (mod->get_bool_attribute(ID::top))
top_mod = mod; top_mod = mod;
pool<RTLIL::Cell*> handled_cells;
if (top_mod != nullptr) { if (top_mod != nullptr) {
worker.flatten_do_list.insert(top_mod->name); worker.flatten_do_list.insert(top_mod->name);
while (!worker.flatten_do_list.empty()) { while (!worker.flatten_do_list.empty()) {
auto mod = design->module(*worker.flatten_do_list.begin()); auto mod = design->module(*worker.flatten_do_list.begin());
while (worker.flatten_module(design, mod, handled_cells)) { } while (worker.flatten_module(design, mod)) { }
worker.flatten_done_list.insert(mod->name); worker.flatten_done_list.insert(mod->name);
worker.flatten_do_list.erase(mod->name); worker.flatten_do_list.erase(mod->name);
} }
} else { } else {
for (auto mod : design->modules().to_vector()) for (auto mod : design->modules().to_vector())
while (worker.flatten_module(design, mod, handled_cells)) { } while (worker.flatten_module(design, mod)) { }
} }
log_suppressed(); log_suppressed();