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rtlil: add fast Cell accessors and SigSpec::const_ratio()

This commit is contained in:
tondapusili 2026-03-13 15:56:55 -07:00
parent 168d64ab19
commit 5d25ae4db6
2 changed files with 43 additions and 4 deletions

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@ -1684,8 +1684,9 @@ public:
bool known_driver() const;
// const_ratio_threshold is expected in [0.0, 1.0]
// boundary is exclusive, returns true only if const bit ratio > const_ratio_threshold
// Constant bit ratio helpers: const_ratio() returns [0.0, 1.0],
// is_mostly_const() returns true if const_ratio() > threshold
double const_ratio() const;
bool is_mostly_const(double const_ratio_threshold = 0.5) const;
bool is_fully_const() const;
bool is_fully_zero() const;
@ -2531,6 +2532,13 @@ public:
void setParam(RTLIL::IdString paramname, RTLIL::Const value);
const RTLIL::Const &getParam(RTLIL::IdString paramname) const;
// Primitive-type parameter accessors for efficient Python interop.
// NOTE: silently truncates wide (>32-bit) parameters and reinterprets string-typed Const values
std::map<std::string, int> getParamsAsInts() const;
// Returns the maximum const_ratio() across all input ports, 0.0 if no input ports
double maxInputConstRatio() const;
void sort();
void check();
void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);