mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Change implicit conversions from bool to Sig* to explicit.

Browse source 
Also fixes some completely broken code in extract_reduce.
This commit is contained in:
Marcelina Kościelnicka 2021-10-21 18:26:47 +02:00
parent 51d42cc917
commit 5cebf6a8ef
2 changed files with 8 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
kernel/rtlil.h
View file

@ -756,7 +756,7 @@ struct RTLIL::SigBit
SigBit(); SigBit();
SigBit(RTLIL::State bit); SigBit(RTLIL::State bit);
SigBit(bool bit); explicit SigBit(bool bit);
SigBit(RTLIL::Wire *wire); SigBit(RTLIL::Wire *wire);
SigBit(RTLIL::Wire *wire, int offset); SigBit(RTLIL::Wire *wire, int offset);
SigBit(const RTLIL::SigChunk &chunk); SigBit(const RTLIL::SigChunk &chunk);
@ -838,7 +838,7 @@ public:
SigSpec(const std::vector<RTLIL::SigBit> &bits); SigSpec(const std::vector<RTLIL::SigBit> &bits);
SigSpec(const pool<RTLIL::SigBit> &bits); SigSpec(const pool<RTLIL::SigBit> &bits);
SigSpec(const std::set<RTLIL::SigBit> &bits); SigSpec(const std::set<RTLIL::SigBit> &bits);
SigSpec(bool bit); explicit SigSpec(bool bit);
SigSpec(RTLIL::SigSpec &&other) { SigSpec(RTLIL::SigSpec &&other) {
width_ = other.width_; width_ = other.width_;

10
passes/techmap/extract_reduce.cc
View file

@ -152,10 +152,10 @@ struct ExtractReducePass : public Pass
log_assert(y.size() == 1); log_assert(y.size() == 1);
// Should only continue if there is one fanout back into a cell (not to a port) // Should only continue if there is one fanout back into a cell (not to a port)
if (sig_to_sink[y[0]].size() != 1) if (sig_to_sink[y].size() != 1 || port_sigs.count(y))
break; break;
x = *sig_to_sink[y[0]].begin(); x = *sig_to_sink[y].begin();
} }
sinks.insert(head_cell); sinks.insert(head_cell);
@ -183,13 +183,15 @@ struct ExtractReducePass : public Pass
continue; continue;
} }
auto xy = sigmap(x->getPort(ID::Y));
//If this signal drives a port, add it to the sinks //If this signal drives a port, add it to the sinks
//(even though it may not be the end of a chain) //(even though it may not be the end of a chain)
if(port_sigs.count(x) && !consumed_cells.count(x)) if(port_sigs.count(xy) && !consumed_cells.count(x))
sinks.insert(x); sinks.insert(x);
//It's a match, search everything out from it //It's a match, search everything out from it
auto& next = sig_to_sink[x]; auto& next = sig_to_sink[xy];
for(auto z : next) for(auto z : next)
next_loads.insert(z); next_loads.insert(z);
} }