diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 4d35e8c42..4982d70ec 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -629,12 +629,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_a);
 					} else {
 						RTLIL::Patch patcher(module, &assign_map);
-						Wire* y = patcher.addWire(NEW_ID, 1);
-						Cell* new_cell = cell->type == ID($xor) ? patcher.addNot(NEW_ID, sig_a, y) : patcher.addNotGate(NEW_ID, sig_a, y);
-						SigSpec sig_y = y;
+						SigSpec sig_y = cell->type == ID($xor) ? patcher.Not(NEW_ID, sig_a) : (SigSpec)patcher.NotGate(NEW_ID, sig_a);
 						int width = cell->type == ID($xor) ? cell->getParam(ID::Y_WIDTH).as_int() : 1;
 						sig_y.append(RTLIL::Const(State::S0, width-1));
-						(void)new_cell;
 						patcher.patch(cell, ID::Y, sig_y);
 					}
 					goto next_cell;